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Mr. Ryota Yasudo gave a presentation in the 9th International Symposium on Networks-on-Chip (NOCS2015)

Ryota Yasudo gave a presentation in the 9th International Symposium on Networks-on-Chip (NOCS’15) entitled “On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck” reporting on ongoing research related to new router architecture.

NOCS is the premier forum for researchers to present their latest findings in the area of Networks-on-Chip.
This year it was held in Vancouver, BC, Canada during September 28-30.
You can view the full manuscript here.

Mr. Akio Nomura and Mr. Hiroshi Nakahara participated in The 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC2015)

1st year Master students Akio Nomura and Hiroshi Nakahara presented part of their research achievement in the 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip. The conference was held in Torino, Italy, September 23-25, 2015. The title of their papers are “3D Shared Bus Architecture Using Inductive Coupling Interconnect” and “Expandable Chip Stacking Method for Many-Core Architectures Consisting of Tiny Chips”. To view the full manuscript, please check the Publication page.

Prof. Hideharu Amano and Mr. Koichiro Masuyama participated in The 25th International Conference on Field-programmable Logic and Applications(FPL2015)

Professor Hideharu Amano and 1st year Master student Koichiro Masuyama presented part of their research achievement in the 25th International Conference on Field-programmable Logic and Applications(FPL2015). The conference was held in London, UK, September 2-4, 2015. The title of their papers are “Reduction Calculator in an FPGA-based Switching Hub for High-performance Clusters” and “7 MOPS/Lemon-battery Image Processing Demonstration with an Ultra Low-power Reconfigurable Accelerator CMA-SOTB-2”. To view the full manuscript, please check the Publication page.

Mr. Takahiro Kaneda participated in The 21st International Conference on Parallel and Distributed Processing Teqchniques and Applications(PDPTA1)

1st year Master student Takahiro Kaneda presented part of his research achievement in the 21st International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA 2015). The conference was held in Las Vegas, USA, July 27-30, 2015. The title of his paper is “Parallel processing of Breadth First Search by Tightly Coupled Accelerators”. To view the full manuscript, please check the Publication page.

Mr. Seiichi Tade participanted in The 26th IEEE International Conference on Application-specific Systems, Architectures and Processors 2015 (ASAP2015)

2nd year Master student Seiich Tade presented part of his research achievement in the 26th IEEE International Conference on Application-specific Systems, Architectures and Processors 2015 (ASAP2015). The conference was held in Toronto, Canada, July 27-29, 2015.
The title of his paper is “A Metamorphotic Network-on-Chip for Various Types of Parallel Applications”. To view the full manuscript, please check the Publication page.

Mr. Hayate Okuhara participated in The International Symposium on Low Power Electronics and Design (ISLPED2015)

2nd year Master student Hayate Okuhara presented part of his research achievement in the IEEE International Symposium on Low Power Electronics and Design 2015 (ISLPED2015). The conference was held in Rome, Italy, July 22-24, 2015.
The title of his paper is “An Optimal Power Supply And Body Bias Voltage for an Ultra Low Power Micro-Controller with Silicon on Thin BOX MOSFET”. To view the full manuscript, please check the Publication page.

Mr. Ryuta Kawano participated in the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP2015)

A doctor candidate student Ryuta Kawano presented part of his research achievement in the 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP2015). The conference was held in Turku – Linnankatu 32 – FI-20100 – Turku – Finland, March 4-6. The title of his research is “Optimized Core-links for Low-latency NoCs”. To view the full manuscript, please check the Publication page.

2015 CUDA programming Contest ranking

Special Coarse on Computer Architecture

Sorry, this entry is only available in Japanese.

2015年度、電子回路基礎、試験問題解答例、成績採点基準決定(Available only in Japanese)

Sorry, this entry is only available in Japanese.