#XILINX= /home/cad/xilinx/ISE-10.1/ISE/verilog/src/glbl.v -y /home/cad/xilinx/ISE-10.1/ISE/verilog/src/unisims +libext+.v

#CP=/home/arena/morisita/hobby/play/verilog/Virtex5/core/
#CORE=$(CP)clockMaker.v

BEHAVIOR= beep.v
TESTBENCH= beep_test.v

VERILOG= vcs +v2k
NCVERILOG= ncverilog +ncaccess+rw

all:
	$(NCVERILOG) $(TESTBENCH) $(BEHAVIOR)
clean:
	rm -rf INCA_libs  csrc waves.* *~ *.log simv* #*
