module memory(
	      CLK,
	      ADDRESS,

	      OUT
	      );

   input CLK;
   input [9:0] ADDRESS;

   output [17:0] OUT;
   reg [17:0] OUT;

   reg [17:0] MEM [1023:0];

   
   always @ (posedge CLK) begin
      OUT <= MEM[ADDRESS];
   end

   initial begin
      $readmemb("data.dat",MEM);
   end
endmodule // memory