UNISIMS= -y /home/cad/xilinx/ISE-10.1/ISE/verilog/src/unisims +libext+.v
SIMPRIMS= -y /home/cad/xilinx/ISE-10.1/ISE/verilog/src/simprims +libext+.v

EXP= result #$B7k2L$r=PNO$9$k%U%)%k%@L>(B
REP= report #$B7k2L$N%m%0$r=PNO$9$k%U%)%k%@L>(B
TOP =top#TOP$B%b%8%e!<%k$NL>A0(B

FPGAPART = -p xc5vsx50t-1-ff1136#FPGA$B$N<oN`$NF~NO(B
IMPLEMENT = -implement moricy_implement.opt#NGDBuild, MAP, PAR, TRACE
CONFIG = -config bitgen#Bitfile$B$N@8@.(B
REPORT = -rd ./$(REP)
EXPORT = -ed ./$(EXP)
#SYNTHESIS = -synth xst_moricy.opt#$B<+J,$G:n$C$?%*%W%7%g%s%U%!%$%k(B(xst$BMQ(B)

#########################################
#		execution		#
#		 command		#
#########################################

XFLOW = xflow $(REPORT) $(EXPORT) $(FPGAPART) $(IMPLEMENT) $(CONFIG) $(TOP)

XLOW2 = xflow $(REPORT) $(EXPORT) $(FPGAPART) $(IMPLEMENT) $(TOP)

all:#$BA4It<B9T(B
	perl xst_443_moricy.pl
	$(XFLOW) 

logic:#$BO@M}9g@.$N$_(B
	perl xst_443_moricy.pl

par:#$BG[CVG[@~$^$G<B9T(B
	perl xst_443_moricy.pl
	$(XFLOW2)

clean:
	rm -rf *.ngc *.ngr *.syr *.ndf *.bld *.xrpt *.log *.lst *.prj *.lso *.ise *~ xlnx_auto_0_xdb/ xst/ INCA_libs/ waves.shm/ *.ncd *.ngd *.pad *.par *.pcf *.ptwx *.twr *.twx *.flw *.bgn *.bit *.drc *.ll *.msk *.unroutes *.xpi *.xst *.map *.mrp *.ngm *.csv *.txt *.xml *.his *.scr report/ result/
