# Script : cts_spec
# Version : V1.0.4
# Function : SOCEncounter FE-CTS spec file
# Date : Dec.18th,2008
# Copyright (C) NEC Electronics Corporation 2005,2007,2008


###MacroModel pin [pin name] maxRiseDelay minRiseDelay maxFallDelay minFallDelay inputCap
#MacroModel pin MEM_0/MEM1_0/OWGB2048W32_0/RAM/BE 5ns 5ns 5ns 5ns 0.01pf

UseSingleDelim YES

#### Modify Top/BottomPreferredLayer
RouteTypeName          clk_upper
PreferredExtraSpace    1
TopPreferredLayer      5
BottomPreferredLayer   4
AssumeShielding        YES
#NonDefaultRule          SP3
End 
RouteTypeName          clk_leaf
PreferredExtraSpace    1
TopPreferredLayer      4
BottomPreferredLayer   3
AssumeShielding        YES
End

#### Global Setting
#DontTouchNet
#+ <net_name>
#DontTouchFromToPin
#+ <instance1_neme/pin_name> <instance2_neme/pin_name>
#GlobalLeafPin
#+ <pin_name> <rising/falling>
#GlobalLeafPort
#+ <port_name> <rising/falling>
#GlobalExcludedPin
#+ <pin_name>
#GlobalExcludedPort
#+ <port_name>
#GlobalThroughPin
#+ <pin_name> <output_pin_name>
#GlobalPreservePin
#+ <input_pin_name>

#### Input constraint file, when use caseanalysis.
#### CTS read only set_case_analysis and set_disable_timing
#TimingConstraintFile case.sdc

### clock net name CLK
#AutoCTSRootPin pll/CLKOUT
AutoCTSRootPin IBUF_CLK/Y
MaxDelay 4.0ns
MinDelay 0.1ns
MaxSkew 250ps
NoGating NO
Obstruction NO
#LevelBalanced YES
ForceMaxCap YES
MaxFanout 100
DetailReport YES
#RootInputTran 0.2ns
BufMaxTran 0.5ns
SinkMaxTran 0.5ns
RouteType clk_upper
LeafRouteType clk_leaf
#PostOpt YES
#OptAddBuffer YES
#OptAddBufferLimit 200
Buffer LDH_BUF_S_10
#LeafBuffer INVXP
MaxCap
+ LDH_BUF_S_10 0.14pf
#+ INVXP 0.11pf
#+ GTDCLXP 0.11pf
DefaultMaxCap 0.14pf
CellHalo
+ LDH_BUF_S_10 6.666 0.550
#LeafPin
#+ AAA/CCC/BE rising
#+ BBB/CCC/BE rising
#ExcludedPin
#+ U_APLL_TOP/U360/B1
#+ U_APLL_TOP/U293/A
#PreservePin
#+ AAA/CCC/A
#+ BBB/CCC/A
#ThroughPin
#+ BBB/DDD/CLK
#PinMaxCap
#+ AAA/BBB/Y 0.5pf
#GatingGrpInstances
#+ cg1/an cg1/i_0
#+ cg2/an cg2/i_0
#GatingGrpModule
#+ grp_module1
#+ grp_a*
End

### clock net name core/reset
#AutoCTSRootPin core/cts_reset/CTS_ROOT/X
AutoCTSRootPin IBUF_RST_N/Y
MaxDelay 4.0ns
MinDelay 0.1ns
MaxSkew 250ps
NoGating rising
Obstruction NO
#LevelBalanced YES
ForceMaxCap YES
MaxFanout 100
DetailReport YES
#RootInputTran 0.2ns
BufMaxTran 0.5ns
SinkMaxTran 0.5ns
RouteType clk_upper
LeafRouteType clk_leaf
#PostOpt YES
#OptAddBuffer YES
#OptAddBufferLimit 200
Buffer LDH_BUF_S_10
#LeafBuffer INVXP
MaxCap
+ LDH_BUF_S_10 0.14pf
#+ INVXP 0.11pf
#+ GTDCLXP 0.11pf
DefaultMaxCap 0.14pf
CellHalo
+ LDH_BUF_S_10 6.666 0.550
#LeafPin
#+ AAA/CCC/BE rising
#+ BBB/CCC/BE rising
#ExcludedPin
#+ U_APLL_TOP/U360/B1
#+ U_APLL_TOP/U293/A
#PreservePin
#+ AAA/CCC/A
#+ BBB/CCC/A
#ThroughPin
#+ BBB/DDD/CLK
#PinMaxCap
#+ AAA/BBB/Y 0.5pf
#GatingGrpInstances
#+ cg1/an cg1/i_0
#+ cg2/an cg2/i_0
#GatingGrpModule
#+ grp_module1
#+ grp_a*
End

