SoC Encounter Digital Flow

このページはSoC Encounter 7.1 を用いて、65nmのプロセスでMUCCRA_TOPを配置配線する方法を示す

はじめに

手順

補足

opcond.tcl
var.tcl
Making SDC
Making .IO file

はじめに

本ページは天野研でMuCCRAチップの試作をFujitsu社の65nmプロセスで SOC Encounterを用いて行った際の設計フローについて説明する。

Cadence社 SoC Encounter 7.1
CS202SNライブラリセットを使用

手順

必要なファイルを用意する

Technology File(.lef): 提供された必要な LEF を用意する

Technology File: cs202_lib/tech/lef/v5.6/CS202/common/12S3G2/tech.lef
   Standard Cell: cs202_sc_io_lib/lef/CS202SN/common/uc.lef
                       IO: 200806RDF/lib/lef/v5.6/CS202/common/common/io.lef
                  RAM: memory/ramcell/lef/v5.6/RAMROM.lef

Timing Library(.lib): 提供されたスタセル、メモリ、IO のMAX,MIN(とTYP)のタイミングファイルを用意する

MAX

Standard Cell(Logic): cs202_sc_io_lib/lib/cs202sn_uc_core_s_p125_105v.lib
     Standard Cell(FF): cs202_sc_io_lib/lib/cs202sn_uc_nscan_s_p125_105v.lib
                                 IO: cs202_sc_io_lib/lib/cs202sn_io_s_p125_m_105v_30v.lib
                            RAM: memory/ramcell/dc/cs202sn_cc_s_p100_11v.lib

MIN

Standard Cell(Logic): cs202_sc_io_lib/lib/cs202sn_uc_core_f_m40_13v.lib
    Standard Cell(FF): cs202_sc_io_lib/lib/cs202sn_uc_nscan_f_m40_13v.lib
                                 IO: cs202_sc_io_lib/lib/cs202sn_io_f_m40_m_13v_36v.lib
                           RAM: memory/ramcell/dc/cs202sn_cc_s_m40_11v.lib

Source File(.v .sdc): 配置配線を行う合成済みの IO 付きの Netlist と SDC を用意する
```
Netlist: MUCCRA_TOP.v
IO File: MUCCRA_TOP.io
   SDC: MUCCRA_TOP.sdc
```

Enconunter の起動

% encounter

Design の読み込み

Design -> Import Design ...
ネットリスト、SDC、IOの位置情報ファイル(.IO)を指定する
タイミングライブラリファイル(.lib)を指定する
AdvanceタブのPowerでVDD VDE VSS VNW VPWを指定する
Capacitance Table Fileを指定する

保存しとけば、次回から入力は不要(.confを読み込む)

conf.confファイル(var.tclファイルは補足を参照)

################################################
#　　　　　　　　　　　　　　　　　　　　　　　 
#  FirstEncounter Input configuration file     
#                                              
################################################
# Created by First Encounter v05.20-s197_1 on Sun Nov  5 17:35:01 2006


source ./scripts/var.tcl

global rda_Input

set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1 -useLefDef56 1 }
set rda_Input(ui_netlist) "${source_dir}/${top_name}.v"
set rda_Input(ui_netlisttype) {Verilog}
set rda_Input(ui_rtllist) ""
set rda_Input(ui_ilmlist) ""
set rda_Input(ui_ilmspef) ""
set rda_Input(ui_settop) {1}
set rda_Input(ui_topcell) "${top_name}"
set rda_Input(ui_celllib) ""
set rda_Input(ui_iolib) ""
set rda_Input(ui_areaiolib) ""
set rda_Input(ui_blklib) ""
set rda_Input(ui_kboxlib) "" 
set rda_Input(ui_oa_oa2lefversion) {}
set rda_Input(ui_view_definition_file) {}
set rda_Input(ui_timelib,min) ${min_lib_file}
set rda_Input(ui_timelib,max) ${max_lib_file}
set rda_Input(ui_timelib) ""
set rda_Input(ui_smodDef) ""
set rda_Input(ui_smodData) ""
set rda_Input(ui_dpath) ""
set rda_Input(ui_tech_file) ""
set rda_Input(ui_io_file) "${source_dir}/${top_name}.io"
set rda_Input(ui_timingcon_file) "${source_dir}/${top_name}_enc.sdc"
set rda_Input(ui_latency_file) ""
set rda_Input(ui_scheduling_file) ""
set rda_Input(ui_buf_footprint) {}
set rda_Input(ui_delay_footprint) {}
set rda_Input(ui_inv_footprint) {}
set rda_Input(ui_leffile) ${lef_file} 
set rda_Input(ui_cts_cell_footprint) {}
set rda_Input(ui_cts_cell_list) {}
set rda_Input(ui_core_cntl) {aspect}
set rda_Input(ui_aspect_ratio) {1.0}
set rda_Input(ui_core_util) {0.7}
set rda_Input(ui_core_height) {1515.4}
set rda_Input(ui_core_width) {1517.54}
set rda_Input(ui_core_to_left) {0}
set rda_Input(ui_core_to_right) {0}
set rda_Input(ui_core_to_top) {0}
set rda_Input(ui_core_to_bottom) {0}
set rda_Input(ui_max_io_height) {0}
set rda_Input(ui_row_height) {0}
set rda_Input(ui_isHorTrackHalfPitch) {0}
set rda_Input(ui_isVerTrackHalfPitch) {1}
set rda_Input(ui_ioOri) {R0}
set rda_Input(ui_isOrigCenter) {0}
set rda_Input(ui_exc_net) ""
set rda_Input(ui_delay_limit) {1000}
set rda_Input(ui_net_delay) {1000.0ps}
set rda_Input(ui_net_load) {0.5pf}
set rda_Input(ui_in_tran_delay) {0.1ps}
set rda_Input(ui_captbl_file) "-typical ${cap_t} -best ${cap_b} -worst ${cap_w}"
set rda_Input(ui_defcap_scale) {1.0}
set rda_Input(ui_detcap_scale) {1.0}
set rda_Input(ui_xcap_scale) {1.0}
set rda_Input(ui_res_scale) {1.0}
set rda_Input(ui_shr_scale) {1.0}
set rda_Input(ui_time_unit) {none}
set rda_Input(ui_cap_unit) {}
set rda_Input(ui_oa_reflib) ""
set rda_Input(ui_oa_abstractname) {}
set rda_Input(ui_oa_layoutname) {}
set rda_Input(ui_sigstormlib) ""
set rda_Input(ui_cdb_file,min) ""
set rda_Input(ui_cdb_file,max) ""
set rda_Input(ui_cdb_file) ""
set rda_Input(ui_echo_file,min) ""
set rda_Input(ui_echo_file,max) ""
set rda_Input(ui_echo_file) ""
set rda_Input(ui_xtwf_file) ""
set rda_Input(ui_qxtech_file) ""
set rda_Input(ui_qxlib_file) ""
set rda_Input(ui_qxconf_file) ""
set rda_Input(ui_pwrnet) {VDD VDE VNW}
set rda_Input(ui_gndnet) {VSS VPW}
set rda_Input(flip_first) {1}
set rda_Input(double_back) {1}
set rda_Input(assign_buffer) {1}
set rda_Input(ui_pg_connections) ""
set rda_Input(ui_gen_footprint) {1}

loadconfig.tcl

# 
##
### Load Configuration file 
##
#

source ./scripts/var.tcl

loadconfig conf.conf 

saveDesign ${top_name}_config.enc

フロアプラン

チップサイズとコアサイズ

チップサイズ、コアサイズを決定する
各サイズはIOの大きさなどを考え決定する
今回はコアエリアが 3420x1320 、コアエリアからIOまでの距離が28

floorplan.tcl

#
##
### Floorplanning 
##
#

set CORE CORE1800

fit
setDrawMode fplan
floorPlan -fplanOrigin center -site ${CORE} -s 3420 1320 28 28 28 28
setRoutingStyle -top -style m
uiSetTool select
fit

End Capacitanceの追加

RAMマクロを配置する前に挿入する
マクロ配置後に挿入すると、マクロの左右にも挿入される
挿入したセル: SC22YUZTAP021

endtap.tcl

#
##
### End Tap
##
#
addEndCap -preCap SC22YUZTAP021 -postCap SC22YUZTAP021 -prefix ENDCAP

ブロックRAMのHaloの追加と配置

RAMマクロ周辺の配置禁止領域（ブロッケージ）を指定する
どれくらい領域をとるかは試行錯誤により決定する

halo.tcl

# 
##
### Edit Halo
##
#
set top_layer    M6
set bottom_layer M1

deletehalofromblock  -allBlock
deleteroutinghalo -allBlocks
redraw

set size 7.5
addRoutingHalo -space ${size} -top ${top_layer} -bottom ${bottom_layer} -allBlocks

set size 9.0
addHaloToBlock ${size} ${size} ${size} ${size} -allBlock
redraw
deselectAll

RAMマクロ等はピンの位置を考慮しながら配置する
あとで電源線を張ったりすると、位置を微調整する必要があるので、適宜位置を変更する
GUI右側の、Instance Pin にチェックを入れとくと、IOやマクロ内のPinが見えるようになる>

MUCCRA_fp.tcl

#
##
### Floorplan
##
#
clearRelativeFPlan
deselectAll
relativeFPlan --relativePlace MUCCRA/COL0/DATA_MEM_BOTTOM_MEM_BANK0_MEM_MACRO TR  BTTOM_CORE_BOUNDARY 
TL 54 340.555 R90
relativeFPlan --relativePlace MUCCRA/COL0/DATA_MEM_BOTTOM_MEM_BANK1_MEM_MACRO TR BOTTOM_CORE_BOUNDARY 
TL 54 610.775 R90
relativeFPlan --relativePlace BAMMA/COL0/DATA_MEM_BOTTOM_CONTEXT_CONT_MEM_CONTEXT_MEM0_MEM_MACRO 
TR  BOTTOM_CORE_BOUNDARY TL 54 880.995 R180
relativeFPlan --relativePlace MUCCRA/COL0/DATA_MEM_TOP_MEM_BANK0_MEM_MACRO TR BOTTOM_CORE_BOUNDARY 
TL 1192.075 340.555 R270
relativeFPlan --relativePlace MUCCRA/COL0/DATA_MEM_TOP_MEM_BANK1_MEM_MACRO TR BOTTOM_CORE_BOUNDARY 
TL 1192.075 610.775 R270
relativeFPlan --relativePlace MUCCRA/COL0/DATA_MEM_TOP_CONTEXT_CONT_MEM_CONTEXT_MEM0_MEM_MACRO TR BOTTOM_CORE_BOUNDARY 
TL 1153.805 880.995 R180
　・
　・
　・
#
##
### Design Save
##
#
if { $enable_save_after_floorplan } {
        saveDesign ${top_name}_floorplan.enc
}

電源回り　

以下に紹介する順番で電源線を張っても、うまくいかない場合があるので注意

電源名とネットの関連付け

VDD VSS VDE VPW VNWとネット名を関連づける（接続する）
Tie High（常に1の信号）と Tie Low （常に0の信号）の接続もここで行う

pgconn.tcl(下記参照)

source ./scripts/var.tcl
#
##
### Specify Global Net Connection (vdd/vss)
##
#

clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -verbose
globalNetConnect VDD -type pgpin -pin VNW -inst * -verbose
globalNetConnect VDD -type tiehi -inst * -verbose
globalNetConnect VSS -type pgpin -pin VSS -inst * -verbose
globalNetConnect VSS -type pgpin -pin VPW -inst * -verbose
globalNetConnect VSS -type tielo -inst * -verbose
globalNetConnect VDE -type pgpin -pin VDE -inst * -verbose

コアリング †

テストランのFeedBackにより、RAMへの電源供給はメッシュにより行うことが推奨

横方向はMETG2(11層)、縦方向はMETG1(10層)を使用、太さは 3、間隔は6.05

corering.tcl

#
##
### For VDD/VSS Core Rings (Single)
##
#
source ./scripts/var.tcl

cutRow
clearCutRow
deselectAll

set offset    1.8
set threshold 0.2
set jdistance 1.8

set spacing   6.05
set width     3.0
set v_layer METG1
set h_layer METG2

addRing \
    -nets { VSS VDD }\
    -around core     \
    -center 1        \
\
    -width_top    ${width} \
    -width_right  ${width} \
    -width_bottom ${width} \
    -width_left   ${width} \
\
    -spacing_top    ${spacing} \
    -spacing_right  ${spacing} \
    -spacing_bottom ${spacing} \
    -spacing_left   ${spacing} \
\
    -offset_top    ${offset} \
    -offset_right  ${offset} \
    -offset_bottom ${offset} \
    -offset_left   ${offset} \
\
    -jog_distance ${jdistance} \
    -threshold    ${threshold} \
\
    -stacked_via_top_layer METTOP  \
    -stacked_via_bottom_layer MET1 \
\
    -layer_top    ${h_layer} \
    -layer_right  ${v_layer} \
    -layer_bottom ${h_layer} \
    -layer_left   ${v_layer}

deselectAll

RAMマクロリング

MET4、MET5で太さ1.6のマクロリングを張る

ramring.tcl

source ./scripts/var.tcl
#
##
### For VDD/VSS rings for RAM (Single)
##
#
deselectAll

set spacing   2.0
set width     1.6
set offset    2.0
set threshold 0.2
set jdistance 1.8

set wire_group_enable    0
set wire_bits            2
set interleaving_enable  1


### Layer
set vlayer MET4
set hlayer MET5

addRing \
    -nets { VDD VSS }  \
    -type block_rings  \
    -around each_block \
\
    -use_wire_group ${wire_group_enable}                \
    -use_wire_group_bits ${wire_bits}                   \
    -use_interleaving_wire_group ${interleaving_enable} \
\
    -width_top    ${width} \
    -width_right  ${width} \
    -width_bottom ${width} \
    -width_left   ${width} \
\
    -spacing_top    ${spacing} \
    -spacing_right  ${spacing} \
    -spacing_bottom ${spacing} \
    -spacing_left   ${spacing} \
\
    -offset_top    ${offset} \
    -offset_right  ${offset} \
    -offset_bottom ${offset} \
    -offset_left   ${offset} \
\
    -jog_distance ${jdistance} \
    -threshold    ${threshold} \
\
    -stacked_via_top_layer METTOP  \
    -stacked_via_bottom_layer MET1 \
\
    -layer_top    ${hlayer} \
    -layer_right  ${vlayer} \
    -layer_bottom ${hlayer} \
    -layer_left   ${vlayer} 


deselectAll
fit
redraw

スタセルのレール

このタイミングでスタセルのレールを引く
次のストライプを先に張った後にレールを引こうとすると、引けないところがでてくる

std_rail.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl
#
##
### Standard Cell PG
##
#

sroute \
    -nets { VSS VDD } \
    -noBlockPins      \
    -noPadRings       \
    -noPadPins        \
    -noStripes        \
    -targetViaTopLayer    11 \
    -crossoverViaTopLayer 11 \
    -layerChangeTopLayer  11 \
    -jogControl { preferWithChanges differentLayer } 
 
fit
redraw

電源メッシュを張る(ストライプ)

メッシュのはりかたの制約の詳細は65nm_SRAM_Power_Rail_Guidline_R1.pdfを参照
層はMET6、太さは1.0、ピッチは30um（メモリが小さいため）
メッシュからRAMへ電源供給を行うため、RAMマクロ上も通過

stripe_through.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl
#
##
### Stripe (Go Through Over Macro)
##
#

set width      1.0
set spacing   2.05
set distance    30
set layer     MET6
set offset      30

addStripe \
    -nets                       { VSS VDD } \
    -layer                       ${layer}   \
    -width                         ${width} \
    -spacing                     ${spacing} \
    -set_to_set_distance        ${distance} \
    -xleft_offset                 ${offset} \
    -merge_stripes_value                0.2 \
    -max_same_layer_jog_length          1.6 \
    -block_ring_top_layer_limit      METTOP \
    -block_ring_bottom_layer_limit     MET1 \
    -padcore_ring_top_layer_limit    METTOP \
    -padcore_ring_bottom_layer_limit   MET1 \
    -stacked_via_top_layer           METTOP \
    -stacked_via_bottom_layer          MET1 \
    -break_stripes_at_block_rings     false

電源IOとコアリングの接続

コアリングから電源IOには11層以上にあるポートと接続を行う(VDD:11,12層 VSS:12層)
コアリングに11層を用いているので、コアリング内側のVSSは12層のみで接続

padpin.tcl

#
##
### For VDD/VSS Pad Pin Connection
##
#
source ./scripts/var.tcl

cutRow
clearCutRow
deselectAll

### Pad pins

sroute \
    -nets { VDD } \
    -noBlockPins  \
    -noPadRings   \
    -noCorePins   \
    -noStripes    \
    -padPinAllGeomsConnect \
    -padPinMinLayer 11     \
    -padPinWidth 6         \
    -jogControl { preferWithChanges differentLayer }


sroute \
    -nets { VSS }\
    -noBlockPins \
    -noPadRings \
    -padPinSkipLeft \
    -noCorePins \
    -padPinSkipRight \
    -noStripes \
    -padPinAllGeomsConnect \
    -padPinMinLayer 12 \
    -padPinWidth 6 \
    -jogControl { preferWithChanges differentLayer } 

sroute \
    -nets { VSS }\
    -noBlockPins \
    -noPadRings \
    -padPinSkipBottom \
    -noCorePins \
    -padPinSkipTop \
    -noStripes \
    -padPinAllGeomsConnect \
    -padPinMinLayer 11 \
    -padPinWidth 6 \
    -jogControl { preferWithChanges differentLayer } 


deselectAll

###
### Design Save
###
if { $enable_save_after_padpin } {
        saveDesign ${top_name}_padpin.enc
}

スタセルの配置と仮配線

TAP セルの挿入

スタセルを置く前に挿入する
SC22YUZTAP021を 30 間隔で挿入
何並列で挿入するかは適宜決定(下の例は11並列)
また同時に SC22YUZCUBAS081 のセルも挿入

tap.tcl

source ./scripts/var.tcl
#
##
### Add Filler
##
#
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 33.8 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 33.4 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 33.0 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 32.6 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 32.2 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 31.8 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 31.4 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 31.0 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 30.6 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 30.2 -prefix WELLTAP
addWellTap -cell SC22YUZTAP021 -maxGap 29.6 -fixedGap -inRowOffset 29.8 -prefix WELLTAP

addWellTap -cell SC22YUZCUBAS081 -maxGap 28.4 -fixedGap -inRowOffset 28.2 -prefix WELLTAP
source ./scripts/pgconn.tcl

スタセル配置

Placement Blockageは1層から6層
スタセルの配置はマルチスレッド化が可能

std_cell_place.tcl

source ./scripts/var.tcl
#
##
### Standard Cell Placement
##
#

deselectAll

source ./scripts/pgconn.tcl

if { $use_multi_threading } {
setReleaseMultiCpuLicense true
setMultiCpuUsage \
    -numThreads             ${num_threads} \
    -numHosts               1 \
    -superThreadsNumThreads ${num_threads} \
    -superThreadsNumHosts   1
} else {
setMultiCpuUsage \
    -numThreads             1 \
    -numHosts               1 \
    -superThreadsNumThreads 1 \
    -superThreadsNumHosts   1
}

setPrerouteAsObs {1 2 3 4 5 6 }

setPlaceMode -reset
setPlaceMode \
    -congEffort            high \
    -timingDriven             1 \
    -modulePlan               1 \
    -doCongOpt                0 \
    -clkGateAware             0 \
    -powerDriven              0 \
    -reorderScan              1 \
    -ignoreSpare              1 \
    -placeIOPins              1 \
    -moduleAwareSpare         0 \
    -checkPinLayerForAccess  {1}\
    -preserveRouting          0 \
    -rmAffectedRouting        0 \
    -checkRoute               1 \
    -swapEEQ                  0

placeDesign -prePlaceOpt  -inPlaceOpt 

if { $use_multi_threading } {
    releaseMultiCpuLicense
}

setDrawView place

source ./scripts/pgconn.tcl

###
### Design Save
###
if { $enable_save_after_std } {
        saveDesign ${top_name}_std.enc
}

仮配線

仮配線は1層から6層まで

trialroute.tcl

source ./scripts/var.tcl
#
##
### Trial Route
##
#

set max_layer 6
set min_layer 1

setTrialRouteMode \
    -floorPlanMode                 false \
    -detour                         true \
    -highEffort                     true \
    -maxRouteLayer          ${max_layer} \
    -minRouteLayer          ${min_layer} \
    -handlePreroute                false \
    -autoSkipTracks                false \
    -handlePartition               false \
    -handlePartitionComplex        false \
    -useM1                         false \
    -keepExistingRoutes            false \
    -ignoreAbutted2TermNet         false \
    -pinGuide                       true \
    -honorPin                      false \
    -selNet                           {} \
    -selNetOnly                       {} \
    -selMarkedNet                  false \
    -selMarkedNetOnly              false \
    -ignoreObstruct                false \
    -PKS                           false \
    -updateRemainTrks              false \
    -ignoreDEFTrack                false \
    -printWiresOnRTBlk             false \
    -usePagedArray                 false \
    -routeObs                       true \
    -routeGuide                       {} \
    -blockageCostMultiple              1 \
    -maxDetourRatio                    0

trialRoute
setDrawView place

タイミング解析とCTS

最初に、仮配線したデザインからRCを抽出する

source ./scripts/var.tcl
source ./scripts/opcond.tcl
extractRC 
delayCal -sdf ${top_name}.sdf -idealclock
wireload -outfile ${top_name}.wl -percent 1.0 -cellLimit 100

Pre-CTS

Setup Time の解析と最適化

pre-CTS.tcl

#
##
### Static Timing Analsysis for preCTS design
##
#
clearClockDomains
setClockDomains -all
timeDesign \
    -preCTS                    \
    -reportOnly                \
    -idealClock                \
    -pathReports               \
    -drvReports                \
    -slackReports              \
    -numPaths 5                \
    -prefix ${top_name}_preCTS \
    -outDir timingReports

###
### pre-CTS optimization
###
clearClockDomains
setClockDomains -all
setOptMode \
    -usefulSkew    false \
    -congOpt       true  \
    -fixDRC        true  \
    -fixFanoutLoad true  \
    -verbose true
optDesign -preCTS -setup -drv

source ./scripts/pgconn.tcl

###
### Design Save
###
if { $enable_save_after_preCTS } {
        saveDesign ${top_name}_preCTS.enc
}

CTS

最初に Gen Spec からクロックツリー用のバッファを選択する

CTS.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl
#
##
### CTS
##
#

source ./scripts/pgconn.tcl

createClockTreeSpec \
    -output Clock.ctstch \
    -bufferList  \
    SC22CKBUFBCLXH1\
    SC22CKBUFBCLXL1\
    SC22CKBUFCLXH1 \
    SC22CKBUFCLXL1 \
    SC22CKBUFCLXP1 \
    SC22CKBUFCLXR1 \
    SC22CKBUFCLXT1 \
    SC22CKINVBCLXH1\
    SC22CKINVBCLXL1\
    SC22CKINVBCLXP1\
    SC22CKINVBCLXR1\
    SC22CKINVBCLXT1\
    SC22CKINVCLXH1 \
    SC22CKINVCLXL1 \
    SC22CKINVCLXP1 \
    SC22CKINVCLXR1 \
    SC22CKINVCLXT1

続く

クロックツリーをはる

set top_prefer_layer    8
set bottom_prefer_layer 3

setCTSMode \
    -traceDPinAsLeaf                      false \
    -traceIoPinAsLeaf                     false \
    -routeClkNet                           true \
    -routeGuide                            true \
    -topPreferredLayer    ${top_prefer_layer}   \
    -bottomPreferredLayer ${bottom_prefer_layer}\
    -routeNonDefaultRule                     {} \
    -useLefACLimit                        false \
    -routePreferredExtraSpace                 1 \
    -opt                                   true \
    -optAddBuffer                          true \
    -moveGate                              true \
    -useHVRC                               true \
    -fixLeafInst                           true \
    -fixNonLeafInst                        true \
    -verbose                              false \
    -reportHTML                           false \
    -addClockRootProp                     false \
    -nameSingleDelim                      false \
    -honorFence                           false \
    -useLibMaxFanout                      true  \
    -useLibMaxCap                         true


clockDesign -specFile Clock.ctstch -outDir clock_report -fixedInstBeforeCTS

setLayerPreference net -isVisible 0
displayClockTree -skew -allLevel -preRoute

###
### Design Save
###
if { $enable_save_after_CTS } {
        saveDesign ${top_name}_CTS.enc
}

Post-CTS

Setup Time / Hold Time の解析と最適化
Setup / Hold のTarget Slackを 0.5 ぐらいに設定

post-CTS.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl

redraw
setLayerPreference net -isVisible 1
#
##
### Trial Route after CTS
##
#
setTrialRouteMode \
    -highEffort            true 
trialRoute


###
### Static Timing Analysis for postCTS design
###
extractRC 
delayCal -sdf ${top_name}.sdf -idealclock
wireload -outfile ${top_name}.wl -percent 1.0 -cellLimit 100

# for design rule and setup time violations
timeDesign \
    -postCTS                          \
    -reportOnly                       \
    -pathReports                      \
    -slackReports                     \
    -numPaths 5                       \
    -prefix ${top_name}_setup_postCTS \
    -outDir timingReports

# for hold time violations
timeDesign \
    -postCTS                         \
    -hold                            \
    -reportOnly                      \
    -pathReports                     \
    -slackReports                    \
    -numPaths 5                      \
    -prefix ${top_name}_hold_postCTS \
    -outDir timingReports


###
### Post CTS Optimization
###
setOptMode \
    -effort             high  \
    -leakagePowerEffort none  \
    -yieldEffort        none  \
    -simplifyNetlist    false \
    -setupTargetSlack   0.5   \
    -holdTargetSlack    0.5   \
    -maxDensity         0.95  \
    -drcMargin          0     \
    -usefulSkew         true
optDesign -postCTS -hold -setup -drv

fit
redraw

source ./scripts/pgconn.tcl

###
### Design Save
###
if { $enable_save_after_postCTS } {
        saveDesign ${top_name}_postCTS.enc
}

本配線

Nanoroute を使用
上位層（10,11,12）は使わない。使うとビアでDRCエラーがでる
なので最大ルーティングレイヤーを9層に設定(Nanorouteの設定の記述はvar.tcl内にある)
Timing Driven は True
Repair Process Antenna Violations もオン（Insert Diodes - Automatic）
Iteration 0
- Initial detailed routing
Iteration 1
- First search-and-repair
iteration 2 - 19
- second to nineteenth search-and-repair
itration 20 - default
- Postroute optimization and additional search-and-repair
下記のスクリプトの前半は並列化の設定

route.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl
#
##
### Routing (Nano Route)
##
#

if { $use_lsf } {
setDistributeHost \
    -lsf          \
    -queue { normal }

setReleaseMultiCpuLicense true
setMultiCpuUsage \
    -numThreads             1 \
    -numHosts               1 \
    -superThreadsNumThreads 1 \
    -superThreadsNumHosts   2
} elseif { $use_ssh } {
setDistributeHost \
    -ssh                      \
    -add ${host1} ${host2} ${host3}

setReleaseMultiCpuLicense true
setMultiCpuUsage \
    -numThreads             1 \
    -numHosts               1 \
    -superThreadsNumThreads 1 \
    -superThreadsNumHosts   ${num_hosts}
} else { # normal
    if { $use_multi_threading } {
        setReleaseMultiCpuLicense true
        setMultiCpuUsage \
            -numThreads             ${num_threads} \
            -numHosts               1 \
            -superThreadsNumThreads ${num_threads} \
            -superThreadsNumHosts   1 
    } else {
        setReleaseMultiCpuLicense true
        setMultiCpuUsage \
            -numThreads             1 \
            -numHosts               1 \
            -superThreadsNumThreads 1 \
            -superThreadsNumHosts   1 
    }
}

source ./scripts/pgconn.tcl


setAttribute -net * -si_post_route_fix true

setNanoRouteMode -drouteAntennaEcoListFile Antenna_list
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithSiPostRouteFix true
setNanoRouteMode -routeSiEffort low

# The router globally routes the design
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeWithSiDriven true
routeDesign -global

# The router does the initial detailed routing 
# (iteration 0 does not include a search-and-repair step), and saves the design as droute0:
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -drouteStartIteration 0
setNanoRouteMode -drouteEndIteration 0
routeDesign -detail
saveDesign droute0.enc

# The router does the first search-and-repair iteration 
# and saves the design for analysis:
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -drouteStartIteration 1
setNanoRouteMode -drouteEndIteration 1
routeDesign -detail
saveDesign droute1.enc

# The router does the second to nineteenth search-and-repair iterations and 
# saves the design for analysis. The switch box grows larger as the iteration number increases.
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -drouteStartIteration 2
setNanoRouteMode -drouteEndIteration 19
routeDesign -detail
saveDesign droute19.enc

# The router runs postroute optimization (drouteEndIteration default) 
# and additional search-and-repair operations and saves the design as droute:
setNanoRouteMode -routeWithTimingDriven true
setNanoRouteMode -routeInsertAntennaDiode true
setNanoRouteMode -drouteUseMultiCutVia true
setNanoRouteMode -routeStrictlyHonorNonDefaultRule true
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -drouteStartIteration 20
setNanoRouteMode -drouteEndIteration default
routeDesign -detail -viaOpt
source ./scripts/pgconn.tcl

saveDesign droute.enc

releaseMultiCpuLicense


###
### Design Save
###
if { $enable_save_after_groute } {
        saveDesign ${top_name}_route.enc
}

ここでDRCエラー（デザイン上に×）翊↑縺ゥ縺ツ後〒縺溘ｉ荳玖ィ倥Eco Route 繧呈焚蝗櫁ゥヲ縺ソ繧/li>

ecoRoute.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl
#
##
### Eco Route
##
#

source ./scripts/pgconn.tcl

deleteroutinghalo -allBlocks

if { $use_multi_threading } {
    setReleaseMultiCpuLicense true
    setMultiCpuUsage \
        -numThreads             ${num_threads} \
        -numHosts               1 \
        -superThreadsNumThreads ${num_threads} \
        -superThreadsNumHosts   1 
} else {
    setReleaseMultiCpuLicense true
    setMultiCpuUsage \
        -numThreads             1 \
        -numHosts               1 \
        -superThreadsNumThreads 1 \
        -superThreadsNumHosts   1 
}

setNanoRouteMode -reset

setNanoRouteMode -routeTopRoutingLayer 9

setNanoRouteMode -routeInsertAntennaDiode true
setNanoRouteMode -routeWithEco true
setNanoRouteMode -drouteStartIteration 0
globalDetailRoute

source ./scripts/pgconn.tcl

setNanoRouteMode -routeWithEco false
setNanoRouteMode -reset

releaseMultiCpuLicense

エラーが消えたらSetup / Hold タイミング解析をして最適化

post-route.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl
#
##
### Post Route 
##
#

#
##
### Timing Analysis
##
#
extractRC 
delayCal -sdf ${top_name}.sdf 
wireload -outfile ${top_name}.wl -percent 1.0 -cellLimit 100

clearClockDomains
setClockDomains -all

###
### Post Route Optimization
###
setOptMode \
    -effort             high  \
    -leakagePowerEffort none  \
    -yieldEffort        none  \
    -simplifyNetlist    false \
    -setupTargetSlack   0.5   \
    -holdTargetSlack    0.5   \
    -maxDensity         0.95  \
    -drcMargin          0     \
    -usefulSkew         true

# for design rule and setup time violations
timeDesign \
    -postRoute                          \
    -reportOnly                         \
    -pathReports                        \
    -slackReports                       \
    -numPaths 5                         \
    -prefix ${top_name}_setup_postRoute \
    -outDir timingReports

optDesign -postRoute -setup -drv


# for hold time violations
timeDesign \
    -postRoute                         \
    -reportOnly                        \
    -hold                              \
    -pathReports                       \
    -slackReports                      \
    -numPaths 5                        \
    -prefix ${top_name}_hold_postRoute \
    -outDir timingReports

optDesign -postRoute -hold  

redraw

source ./scripts/pgconn.tcl

###
### Design Save
###
if { $enable_save_after_postroute } {
        saveDesign ${top_name}_postRoute.enc
}

Filler セルの挿入

挿入するセルは SC22YUZS021 SC22YUZS011

filler.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl
#
##
### Add Filler
##
#

source ./scripts/pgconn.tcl

getFillerMode 
findCoreFillerCells
addFiller -cell SC22YUZS021 SC22YUZS011 -prefix FILLER -markFixed

source ./scripts/pgconn.tcl

チェック

ここで無視できないエラーがでたらなんとかして消す

Verify Anntena

check.tcl

source ./scripts/var.tcl
source ./scripts/opcond.tcl
#
##
### Verify
##
#

clearDrc

###
### Verify Antenna
###

verifyProcessAntenna -reportfile ${top_name}.antenna.rpt -leffile ${top_name}.antenna.lef -error 1000
続く

Verify Connectivity

IOの電源回りでエラーがでるが無視

###
### Verify Connectivity
###
verifyConnectivity -type all -error 1000 -warning 50
続く

Verify Geometry

電源IOでエラーがたくさんでるため、表示エラー数を1万にする。これは無視してOK
可能であればCPU数を2、3にすると早い

###
### Verify Geometry
###
verifyGeometry -antenna -error 10000 -cpu 3
続く

Check Design

###
### Check Design
###
checkDesign -io -netlist -physicalLibrary -powerGround -tieHilo -timingLibrary -floorplan -place -outdir checkDesign
続く

おまけ

###
### Gate Count
###
reportGateCount -level 5 -limit 100 -outfile ${top_name}.gateCount

###
### Report Summary
###
summaryReport -outdir summaryReport

GDS / Netilist の生成

SDF、Netlist、GDSを出力する

save.tcl

source ./scripts/var.tcl
#
##
### Save
##
#
source ./scripts/pgconn.tcl

# StreamOut setting.
setStreamOutMode -SEcompatible ON -SEvianames ON

### GDS out
streamOut ${top_name}.gds     \
    -mapFile gds2.map   \
    -libName DesignLib        \
    -structureName ${top_name}\
    -stripes               1  \
    -units              1000  \
    -mode                ALL


saveNetlist ${top_name}.v
saveNetlist ${top_name}.v.lvs -includePhysicalInst
write_sdf -version 3.0 -edges noedge -nonegchecks ${top_name}.sdf


### Save
saveDesign ${top_name}.enc

補足

opcond.tcl

Operating Condition

setOpCond -maxLibrary  cs202sn_uc_core_s_p125_105v -max DEFAULT -minLibrary cs202sn_uc_core_f_m40_13v -min DEFAULT

var.tcl

Global変数の設定
Pathの設定
Save Pointのフラグの設定
LSF,SSH Distribution,Multi-threadingの設定

###
### Technology Settting
###

# true: 12-metal false: 7-metal

set use_12tech_file true


###
### Global Variables
###


# Top Module Name
set top_name  "MUCCRA_TOP"

#set lib_home_dir "/home/vdec/lib/fujitsu65/cs202_sc_io_lib/lib"
#set lib_ram_dir  "/home/vdec/lib/fujitsu65/memory/muccra/ramcell/dc"

set lib_dir    "./lib"
set lef_dir    "./lef_file"
set gds_dir    "./gds"
set source_dir "./srcNet"

set max_lib_file "      ${lib_dir}/cs202sn_uc_nscan_s_p125_105v.lib 
                        ${lib_dir}/cs202_io_s_p125_m_105v_30v.lib 
                        ${lib_dir}/cs202_cc_s_p100_11v.lib
                        ${lib_dir}/cs202sn_uc_core_s_p125_105v.lib"


set min_lib_file "      ${lib_dir}/cs202sn_uc_nscan_f_m40_13v.lib 
                        ${lib_dir}/cs202_io_f_m40_m_13v_36v.lib 
                        ${lib_dir}/cs202_cc_s_m40_11v.lib
                        ${lib_dir}/cs202sn_uc_core_f_m40_13v.lib "

set cap_t "${lib_dir}/basic.capTbl.typ"
set cap_b "${lib_dir}/basic.capTbl.best"
set cap_w "${lib_dir}/basic.capTbl.worst"

set lef_file "          ${lef_dir}/tech_12S3G2.lef 
                        ${lef_dir}/uc_CS202SN.lef 
                        ${lef_dir}/io.lef 
                        ${lef_dir}/RAMROM.lef"

###
### Save Point
###
set enable_save_after_floorplan 0
set enable_save_after_padpin    1
set enable_save_after_std       1
set enable_save_after_preCTS    1
set enable_save_after_CTS       1
set enable_save_after_postCTS   1
set enable_save_after_sroute    1
set enable_save_after_groute    1
set enable_save_after_postroute 1
set enable_save_after_filler    1
set enable_save_after_finish    1


###
### Boost Option
###

# LSF Distribution
#
# <** WARNING **>This option is currently unavailable
# <** WARNING **>LSF is not working correctly
#
# Only Available on Host : hogehoge
#
# This option is used in Nanoroute(route.tcl)
set use_lsf false

# SSH Distribution
# 
# This option uses other machines
# You can identify many machines, but be careful
# someone uses specified machine
#
# If you specified more than 3 machines
# You need to change route.tcl file also
#
# This option is used in Nanoroute(route.tcl)
set use_ssh     false

set num_hosts      3
set host1     host1
set host2     host2
set host3     host3
#set host4  

# Multi-Threading
#
# <** WARNING **>This option sometime down the Encounter
#
# This option is available in Standard Cell Placement(std_cell_place.tcl)
set use_multi_threading true
set num_threads 3

### Nano Route Option
setNanoRouteMode -reset

setNanoRouteMode -routeTopRoutingLayer 9

## nanoroute setting. (drc/ant)
setNanoRouteMode -dbAutoBlockCoverPin true
setNanoRouteMode -dbSkipAnalog true
setNanoRouteMode -drouteAllowMergedWireAtPin false
setNanoRouteMode -drouteConnectTieNetCutNumber 2
#setNanoRouteMode -drouteConnectTieNetCutNumber 4
#setNanoRouteMode -drouteConMinimizeViaCount true
setNanoRouteMode -drouteExpAlignWireEdgeWithPin true
setNanoRouteMode -drouteHonorStubRuleForBlockPin true
setNanoRouteMode -drouteUseMinSpacingForBlockage false
setNanoRouteMode -drouteViaOnGridOnly true
setNanoRouteMode -routeExtraViaEnclosure "0.250"
#setNanoRouteMode -routeExpAutoOptimalGgrids true
setNanoRouteMode -routeAutoGgrid true
setNanoRouteMode -routeIgnoreAntennaTopCellPin false
setNanoRouteMode -routeMergeSpecialWire true
setNanoRouteMode -routeStrictlyHonorNonDefaultRule true
setNanoRouteMode -routeStripeLayerRange "1:5"
setNanoRouteMode -routeWithViaInPin true
setNanoRouteMode -routeWithViaOnlyForStandardCellPin true
## nanoroute setting. (dfm)
setNanoRouteMode -drouteUseMultiCutViaEffort high
#####################setNanoRouteMode -routeWithLithoDriven true

setAttribute -net * -si_post_route_fix true

setNanoRouteMode -drouteAntennaEcoListFile Antenna_list
setNanoRouteMode -routeWithSiDriven true
setNanoRouteMode -routeWithSiPostRouteFix true
setNanoRouteMode -routeSiEffort low

Making SDC

Design Compilerで作成したSDCファイルの一部のコマンドはEncounterでサポートしていないので修正／削除する必要がある

set_units -time ps -resistance Ohm -capacitance pF -voltage V -current mA
↓
set_time_unit ps

set_operating_conditions -max DEFAULT -max_library cs202sn_uc_core_s_p125_105v\
                                               -min DEFAULT -min_library cs202sn_uc_core_f_m40_13v
↓
setOpCond -maxLibrary  cs202sn_uc_core_s_p125_105v -max DEFAULT -minLibrary cs202sn_uc_core_f_m40_13v -min DEFAULT

すべての入力ポートについて

set_driving_cell -lib_cell SC22INVXA1 -library cs202sn_uc_core_s_p125_105v  [get_ports {MUCCRA_ADDR[10]}]
↓
set_driving_cell -lib_cell SC22INVXA1 [get_ports {MUCCRA_ADDR[10]}]

削除（またはコメントアウト）するのは以下のコマンド

#set_max_area 0
#set_ideal_network [get_ports CLK]
#set_ideal_network [get_ports RST_N]

Making .IO file

TDFファイルを書くか、.IOファイルを書くか、どちらでもよいが、今回は.IOファイルを作成
ここらへんはスクリプト化して作成できるようにしておくと、変更があったときがラク
下のCORNER_SW、IO_CLK_B0、VDD_00などはMUCCRA_TOP.v内のトップモジュールでインスタンス化されたIOたち
今回12層のIOに対応するため、IOを重ねている。そのため、良くみるとOffsetを同じにして重ねている

Orient: R180
Offset: 0 
Pad: CORNER_SW SW
Orient: R180
Offset: 170
Pad: F1_0 S
Orient: R180
Offset: 171
Pad: F2_0 S
Orient: R180
Offset: 173
Pad: F5_0 S

Orient: R180
Offset: 178
Pad: IO_CLK_B0 S
Orient: R180
Offset: 178
Pad: IO_CLK_B0_TOP S

Orient: R180
Pad: F20_0 S
Orient: R180
Offset: 238
Pad: IO_RST_N0 S
Orient: R180
Offset: 238
Pad: IO_RST_N0_TOP S

Orient: R180
Pad: F20_1 S
Orient: R180
Offset: 298
Pad: IO_MUCCRA_ADDR10 S
Orient: R180
Offset: 298
Pad: IO_MUCCRA_ADDR10_TOP S

Orient: R180
Pad: F20_2 S
Orient: R180
Offset: 358
Pad: IO_MUCCRA_ADDR9 S
Orient: R180
Offset: 358
Pad: IO_MUCCRA_ADDR9_TOP S

Orient: R180
Pad: F5_1 S
Orient: R180
Pad: F10_0 S
Orient: R180
Offset: 413
Pad: VDD_00 S
Orient: R180
Offset: 413
Pad: VDD_00_TOP S
・
・
・