Y.Saito, T.Sano, M.Kato, V.Tunbunheng, Y.Yasuda, M.Kimura, H.Amano, “MuCCRA-3: A low power dynamically Reconfigurable Processor Array”, In Proceedings of Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific, pp.377 - 378, Jan.2010.

M.Kimura, Y.Saito, T.Sano, M.Kato, V.Tunbunheng, Y.Yasuda, H.Amano, “Low power image processing using MuCCRA-3: A Dynamically Reconfigurable Processor Array”, In Proceedings of International Conference on Field Programmable Technology (ICFPT 2009), pp.364 - 367, Dec. 2009.

M.Kato, T.Sano, Y.Yasuda, Y.Saito and H.Amano, “A Study on Interconnection Networks of the Dynamically Reconfigurable Processor Array MuCCRA”, In Proceedings of International Conference on Field Programmable Technology (ICFPT 2009), pp.415 - 418, Dec. 2009.

Hideharu Amano “Japanese Dynamically Reconfigurable Processors” In Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA2009), pp.19-28, July 2009.(Invited Paper)

T.Sano, Y.Saito, H.Amano “Configuration with Self-configured Datapath: A high speed configuration method for Dynamically Reconfigurable Processors” In Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA2009), pp.283-286, July 2009.

Y.Saito, T.Sano, M.Kato, V.Tunbunheng, Y.Yasuda, H.Amano “Configuration with Self-configured Datapath: A high speed configuration method for Dynamically Reconfigurable Processors” In Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA2009), pp.112-118, July 2009.

Y.Kohama, Y.Sugimori, S.Saito, Y.Hasegawa, T.Sano, K.Kasuga, Y.Yoshida, K.Niitsu, N.Miura, H.Amano, T.Kuroda “A Scalable 3D Processor by Homogeneous Chip Stacking with Inductive-Coupleing Link” In Proceedings of International Simposia on VLSI Technology and Circuits, June 2009.

T.Nakamura, T.Sano, Y.Hasegawa, S.Tsutsumi, V.Tunbunheng, H.Amano “Exploring the optimal size for multicasting configuration data of Dynamically Reconfigurable Processors” In Proceedings of International Conference on Field Programmable Technology (ICFPT2008), December 2008.

Y.Saito, T.Shirai, T.Nakamura, T.Nishimura, Y.Hasegawa, S.Tsutsumi, T.Kashima, M.Nakata, S.Takeda, K.Usami, H.Amano “Leakage Power Reduction For Coarse Grained Dynamically Reconfigurable Processor Arrays With Fine Grained Power Gating Technique” In Proceedings of International Conference on Field Programmable Technology (ICFPT2008), December 2008.

Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa and Hideharu Amano “Power reduction techniques for Dynamically Reconfigurable Processor Arrays” In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL2008), September 2008.

Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa and Hideharu Amano “Instruction Buffer Mode for Multi-Context Dynamically Reconfigurable Processors” In Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL2008), September 2008.

Masaru Kato, Yohei Hasegawa and Hideharu Amano “Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs” In Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA2008), pp.215-220, July 2008.

S.Tsutsumi V.Tunbunheng Y.Hasegawa T.Nakamura T.Nishimura H.Amano “Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays” In Proceedings of International Conference on Field Programmable Technology (ICFPT2007), pp.273-276, December 2007.

Vasutan Tunbunheng and Hideharu Amano. “Black-Diamond: a Retargetable Compiler using Graph with Configuration Bits for Dynamically Reconfigurable Architectures (Outstanding Paper Award)” In Proceedings of Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI2007), pp.412-419, December 2007.

H.Amano Y.Hasegawa S.Tsutsumi T.Nakamura T.Nishimura V.Tunbunheng A.Parimala T.Sano M.Kato “MuCCRA chips: Configurable Dynamically-Reconfigurable Processors” Asian Solid-State Circuit Conference (ASSCC2007), pp. 384-387, Jeju, Korea, November 2007.

Y.Hasegawa S.Tsutsumi V.Tunbunheng T.Nakamura T.Nishimura H.Amano ” Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays” In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL2007), pp.796-799, August 2007.

Vasutan Tunbunheng, Masayasu Suzuki, and Hideharu Amano. “Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices”, IEICE Transactions on Information and Systems, Vol.E90-D, No.2, pp.473-4 81, Feburary 2007.

Hideharu Amano. “A Survey on Dynamically Reconfigurable Processors”, IEICE Transactions on Communications, Vol.E89-B, No.12, pp.3179-3187, December 2006.

Hideharu Amano, Akiya Jouraku, Kenichiro Anjo. “A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor”, IEICE Transactions, Vol.E86-B, No. 12, pp.3385-3391, 2003. [PDF]

Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, and Hideharu Amano. An Adaptive Viterbi Decoder on the Dynamically Reconfigurable Processor. In Proceedings of International Conference on Field Programmable Technology (FPT2006), pp. 285-288, Bankok, Thailand, December 2006.

Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Syunsuke Kurotaki, Takuro Nakamura, and Takashi Nishimura. “A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors”. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL2006), pp. 575-580, August 2006.

Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, and Hideharu Amano. “Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor”. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006) / Reconfigurable Architectures Workshop (RAW2006), April 2006.

Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, and Hideharu Amano. “A Cost-Effective Context Memory Structure for Dynamically Reconfigurable Processors”. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006) / Reconfigurable Architectures Workshop (RAW2006), April 2006.

Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, and Hideharu Amano. “Adaptive Computing on the Dynamically Reconfigurable Processor”. In Proceedings of International Conference on Cool Chips IX, pp. 409-421, April 2006.

Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura and Hideharu Amano. “Performance/Cost trade-off evaluation for the DCT implementation on the Dynamically Reconfigurable Processor.” In Proceedings of International Workshop on Applied Reconfigurable Computing (ARC2006), March 2006.

Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Kenichiro Anjo, Toru Awashima, and Hideharu Amano. “An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor.” In Proceedings of International Conference on Field Programmable Technology (FPT2005), pp. 163-170, December 2005.

Hideharu Amano, Shohei Abe, Katsuaki Deguchi, and Yohei Hasegawa. “An I/O mechanism on a Dynamically Reconfigurable Processor -Which should be moved: Data or Configuration?-.” In Proceedings of International Conference on Field Programmable Logic and Application (FPL2005), pp. 347-352, August 2005.

Shunsuke Kurotaki, Noriaki Suzuki, Kazuhiro Nakadai, Hideharu Amano. “Implementation of Active Direction-Pass Filter on Dynamically Reconfigurable Processor.” In Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS-2005), pp. 215-220, August 2005.

Shohei Abe, Yohei Hasegawa, and Hideharu Amano. “Implementation of AES on the Dynamic Reconfigurable Processor”, COOL Chips VIII, poster session, April 2005.

Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi and Masayasu Suzuki. “Performance and Cost Analysis of Time-multiplexed Execution on the Dynamically Reconfigurable Processor”, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM2005), poster session, April 2005.

Katsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, and Hideharu Amano. “Implementing Core Tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor”, Proceedings of the Workshop on Dynamically Reconfigurable Systems (ARCS2005-DRS), pp.12-18, March 2005.

Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, and Hideharu Amano. “Time-multiplexed Execution on the Dynamically Reconfigurable Processor -A Performance/ Cost Evaluation-”, Proceedings of International Symposium on Field-Programmable Gate Arrays (FPGA2005), pp. 265, February 2005.

Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, and Toru Awashima. “Stream Applications on the Dynamically Reconfigurable Processor,” Proceedings of International Conference on Field Programmable Technology(FPT2004), pp.137-144, December 2004.

Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, and Masayasu Suzuki. “Techniques for Virtual Hardware on a Dynamic Reconfigurable Processor -An approach to tough cases-”, Proceedings of International Conference on Field Programmable Logic and Application(FPL2004), pp.464-473, September 2004.

Noriaki Suzuki, Syunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, and Toru Awashima. “Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor”, Proceedings of International Conference on Field-Programmable Custom Computing Machines(FCCM2004), poster session, April 2004.

Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Katsuaki Deguchi, Kenichiro Anjo, Toru Awashima, and Hideharu Amano. “Stream Application Evaluation on the DRP-1”, Proceedings of International Conference on COOL Chips VII, pp.33-47, April 2004.

Toshiro Kitaoka, Hideharu Amano, and Kenichiro Anjo. “Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device”, Proceedings of International Conference on Field Programmable Logic and Application(FPL2003), pp.171-180, September 2003.

Hideharu Amano, Akiya Jouraku, and Kenichiro Anjo. “A dynamically adaptive switching fabric on a multicontext reconfigurable device”, Proceedings of International Conference on Field Programmable Logic and Application(FPL2003), pp.161-170, September 2003.

Yutaka Yamada, Katsuaki Deguchi, Naoto Kaneko, and Hideharu Amano. “Core Processor / Multicontext Device Co-design”, COOL Chips VI, poster session, April 2003.

Masaki Uno, Yuichiro Shibata and Hideharu Amano: “Implementation of Data Driven Applications on a Multi-context Reconfigurable Device,”IEICE Transactions on Information and Systems, Vol. E86-D, No.5, pp.841-849, May 2003.

Naoto Kaneko and Hideharu Amano: “A General Hardware Design Model for Multicontext FPGAs”, Proceedings of the International Conference of Field-Programmable Logic and Applications, Sept. 2002.

Daisuke Kawakami, Yuichiro Shibata and Hideharu Amano: “A Prototype Chip of Multicontext FPGA with DRAM for Virtual Hardware,” Asia and South Pacific Design Automation Conference, pp. 17-18, Feb. 2001.

H. Amano, Y. Shibata and M. Uno: “Reconfigurable System: New Activities in Asia,” Proceedings of the International Workshop on Field-Programmable Logic and Applications, pp.585-594, Aug. 2000.

O. Yamamoto, Y. Shibata, H. Kurosawa, H. Amano: “A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems,” Proceedings of the International Workshop on Field-Programmable Logic and Applications, pp.475-484, Aug. 2000.

A. Takayama, Y. Shibata, K. Iwai and H. Amano: “Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System,” Proceedings of the International Workshop on Field-Programmable Logic and Applications, pp.685-694, Aug. 2000.

M. Uno, Y. Shibata, H. Amano, K. Furuta, T. Fujii and M. Motomura: “Implementation of Virtual Hardware on Dynamically Reconfigurable Logic,” Proceedings of the Joint Conference of the World Multiconference on Systemics, Cybernetics and Informatics & the International Conference on Information Systems, Analysis and Synthesis, pp.124-129, Jul. 2000.

Y. Shibata, M. Uno, H. Amano, K. Furuta, T. Fujii and M. Motomura: “A Virtual Hardware System on a Dynamically Reconfigurable Logic Device,” Proceedings of the International Conference on FPGAs for Custom Computing Machines, Apr. 2000.

Y. Shibata, X.-P. Ling and H. Amano: “Internal Parallelization of Data-driven Virtual Hardware,” Proccedings of the International Conference on Parallel Processing Workshops, pp.366-371, Sep. 1999.

A. Takayama, Y. Shibata, K. Iwai, H. Miyazaki, K. Higure, X.-P. Ling and H. Amano: “Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System,” Proccedings of the International Conference on Parallel Processing Workshops, pp.346-351, Sep. 1999.

H. Miyazaki, Y. Shibata, A. Takayama, X.-P. Ling and H. Amano: “Emulation of Multichip WASMII on Reconfigurable System Testbed FLEMING,” Proceedings of the International Conference on Parallel Architectures and Compilation Techniques Workshop on Reconfigurable Computing, pp.47-52, Oct. 1998.

Y. Shibata, H. Miyazaki, X.-P. Ling and H. Amano: “HOSMII: A Virtual Hardware Integrated with DRAM,” Proceedings of the Merged Symposium of the International Parallel Processing Symposium & the Symposium on Parallel and Distriubted Processing Workshops, (Lecture Notes in Computer Science 1388), pp.85-90, Mar. 1998.

H. Amano and Y. Shibata: “Reconfigurable Systems: Activities in Asia and South Pacific,” Proceedings of the Asia and South Pacific Design Automation Conference, pp.453-457, Feb. 1998.

Y. Shibata, H. Miyazaki, X.-P. Ling and H. Amano: “Toward the Realistic Virtual Hardware,” Proceedings of the International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, pp.50-55, Oct. 1997.

O. Yamamoto, Y. Shibata, H. Kurosawa and H. Amano: “A Reconfigurable Markov Chain Simulator for Analysis of Parallel Systems,” Proceeding of the IEEE International Conference on Innovative Systems in Silicon, Sep. 1997.

K. Nukata, Y. Shibata, H. Amano and Y. Anzai: “A Reconfigurable Sensor-Data Processing System for Personal Robots,” Proceedings of the International Workshop on Field-Programmable Logic and Applications (Lecture Notes in Computer Science 1304), pp.491-500, Sep. 1997.

X.-P. Ling, Y. Shibata, H. Miyazaki, H. Amano, and K. Higure: “Total System Image of the Reconfigurable Machine WASMII,” Procceedings of the International Conference on Parallel Distributed Processing Techniques and Applications, pp.1092-1096, Jun. 1997.

Y. Shibata, X.-P. Ling and H. Amano: “An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware,” Proceedings of the International Workshop on Field-Programmable Logic and Applications, (Lecture Notes in Computer Science 1142), pp.253-276, Sep. 1996.

X.-Y. Chen, X.-P. Ling and H. Amano: “Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware,” Procceedings of the International Workshop on Field-Programmable Logic and Applications, (Lecture Notes in Computer Science 849), pp.208-219, Sep. 1994.

X.-P. Ling and H. Amano: “Performance Evaluation of WASMII: A Data Driven Computer on a Virtual Hardware,” Proceedings of the International PARLE Conference (Lecture Notes in Computer Science 694), pp.610-621, Jun. 1993.

X.-P. Ling and H. Amano: “WASMII: A Data Driven Computer on a Virtual Hardware,” Proceedings of the IEEE International Symposium on FPGAs for Custom Computing Machines, pp.33-42, Apr. 1993.