Japanese here. Lynx is recomended.
Last modified: Wed Nov 11 13:03:23 JST 1998

ATTEMPT group home page

ATTEMPT = A Typical Testing Environment of Multi Processor sysTems

Members

Our study

Background --- on-chip multiprocessor

A high performance microprocessor which issues multiple instructions has been implemented. However, the performance improvement of such microprocessors will become difficult because of its complicated structure and limitation of instruction level parallelism. To utilize silicon resources efficiently, a on-chip multiprocessor has been widely researched.

Snoop cache protocol for on-chip multiprocessor

In such a on-chip multiprocessor, architectural trade-off is completely different from current bus connected multiprocessors. The speed of shared bus inside the chip will become far faster than that of the backplane bus. But on the other hand, the large gap of the transfer bandwidth between inside and outside of the chip will become a substantial problem. We proposed New Keio protocol which optimized for an on-chip multiprocessor.

Emulation and evaluation machine --- ATTEMPT-1

To evaluate performance of protocols by larger application and operating system, real machine is nesessary. For this reason, a reconfigurable multiprocessor testbed ATTEMPT-1 is proposed. By using programmable devices (CPLDs and FPGAs) in the core of the cache system, various parameters of the cache and bus system are selectable. Since the each core of controller is described in the HDL (Hardware Description Language) and implemented on CPLD, cache protocols and bus protocols can be changed just by rewriting description on the state transitions. By using high speed FPGAs in the data path, enough high speed (25MHz clock) is kept in spite of its flexibilty.

New cache architecture for on-chip multiprocessor

In order to increase effective utilization of on-chip cache memory of such a on-chip multiprocessor, pSAS(pseudo Set Associative ans Shared) cache is proposed. In this cache, cache module with snoop mechanism attached to the other processor in the same chip can be used as an extra way of its own cache. It combines advantages of both snoop and shared cache.

Libraries

ATTEMPT group / attempt@am.ics.keio.ac.jp