/*
 *	test.sfl
 */

module test {

declare ppico16 {
	input		idata<16>, ddatain<16>;
	output		iaddr<16>, daddr<16>, ddataout<16>;
	output		dmoe, dmwe;
	instrin		enable;
	instr_arg	enable(idata, ddatain);
}

declare memory {
	input		ad<16>;
	input		di<16>;
	input		we<2>;
	output		do<16>;
	instrin		enable;
	instr_arg	enable(ad, di, we);
}

instrin		enable;

ppico16		PICO;
memory		IMEM, DMEM;

sel_v	dwrite<16>, dread<16>, iread<16>, iaddr<16>, daddr<16>, dwe; 

instruct enable par {
	PICO.enable(iread, dread);
	iread = IMEM.enable(iaddr<15:0>, 0x0000, 0b11).do;
	dread =	DMEM.enable(daddr<15:0>,dwrite, dwe||dwe).do;
	iaddr = PICO.iaddr;
	dwe = ^PICO.dmwe;
	any {
	PICO.dmwe:
		par { daddr = PICO.daddr; dwrite = PICO.ddataout; }
	PICO.dmoe:
		par { daddr = PICO.daddr; dwrite = 0x0000; }
	else:
		par { daddr = 0x0000; dwrite = 0x0000; }
	}
}

} /* test */

circuit memory {
	input		ad<16>;
	input		di<16>;
	input		we<2>;
	output		do<16>;
	instrin		enable;

	mem		memory[65536]<8>;
	instruct enable par {
		do =  memory[ad & 0b1111111111111110] || memory[ad | 0b0000000000000001] ;
		alt {^we<0>: memory[ad & 0b1111111111111110] := di<15:8>; }
		alt {^we<1>: memory[ad | 0b0000000000000001] := di<7:0>; }
	}

} /* memory */