/* * test.sfl */ declare ppico16 { input idata<16>, ddatain<16>, int_req; output iaddr<16>, daddr<16>, ddataout<16>; output dmoe, dmwe; instrin enable; instr_arg enable(idata, ddatain, int_req); } declare memory { input ad<10>; input di<16>; input we<2>; output do<16>; instrin enable; instr_arg enable(ad, di, we); } declare iomodel { input set; input di<16>; input sel; input read; output do<16>; output setflag; instrin enable; instr_arg enable(set, di, sel, read); } module test { input ioset; input iodata<16>; instrin enable; ppico16 PICO; memory IMEM, DMEM; iomodel IO; sel_v dwrite<16>, dread<16>, iread<16>, iaddr<16>, daddr<16>, dwe; instruct enable par { PICO.enable(iread, dread, IO.setflag); iread = IMEM.enable(iaddr<9:0>, 0x0000, 0b00).do; DMEM.enable(daddr<9:0>,dwrite, dwe||dwe); IO.enable(ioset, iodata, daddr<1>, PICO.dmoe & daddr<15>); alt {^daddr<15>: dread = DMEM.do; else: dread = IO.do; } iaddr = PICO.iaddr; dwe = PICO.dmwe; any { PICO.dmwe: par { daddr = PICO.daddr; dwrite = PICO.ddataout; } PICO.dmoe: par { daddr = PICO.daddr; dwrite = 0x0000; } else: par { daddr = 0x0000; dwrite = 0x0000; } } } } /* test */ circuit memory { input ad<10>; input di<16>; input we<2>; output do<16>; instrin enable; mem memory[1024]<8>; instruct enable par { do = memory[ad & 0b1111111110] || memory[ad | 0b0000000001] ; alt {we<0>: memory[ad & 0b1111111110] := di<15:8>; } alt {we<1>: memory[ad | 0b0000000001] := di<7:0>; } } } /* memory */ module iomodel { input set; input di<16>; input sel; input read,rst; output do<16>; output setflag; instrin enable; reg_wr flag,dreg<16>; reg_ws setdelay; instruct enable par { setdelay:= set; setflag = flag; alt { sel & read : do = dreg; ^sel & read : do = 0b000000000000000 || flag; else: do = 0x0000;} alt { set & ^setdelay : par { dreg := di; flag := 0b1; } sel & read : flag := 0b0; } } }