/*
 *	test.sfl
 */

declare pico16 {
	input		datain<16>;
	input		int_req;
	input		rst;
	input		memok;
	output		dataout<16>;
	output		address<16>;
	instrout	oe, we0, we1;
	instrin		enable;
	instr_arg	enable(datain, int_req, rst, memok);
}

declare cache {
	input       rst, cpuadr<10>, cpuwd<16>, cpuwe0, cpuwe1, cpuoe;
	output      cpurd<16>,cpumemok;
	instrin     enable;
	instr_arg enable(rst, cpuadr, cpuwd, cpuwe0, cpuwe1, cpuoe); }

declare iomodel {
	input		set;
	input		di<16>;
	input		sel;
	input		read, rst;
	output do<16>;
	output setflag;
	instrin		enable;
	instr_arg enable(set, di, sel, read, rst);
}

module test {

input ioset;
input iodata<16>;
input rst;
instrin enable;
pico16		PICO;
cache		MEM;
iomodel		IO;

sel		mout<16>; /* memory output */
sel		intrq; 
sel		memok;

instruct enable par {
	PICO.enable(mout, intrq, rst, memok);
	MEM.enable(rst, PICO.address<9:0>, PICO.dataout,PICO.we0,PICO.we1,PICO.oe);
	intrq = IO.enable(ioset, iodata, PICO.address<1>, 
			PICO.oe & PICO.address<15>, rst).setflag;
	alt {
	^PICO.address<15> : par{
			mout = MEM.cpurd; 
			memok = MEM.cpumemok;}
	else: 
		alt { PICO.oe: par {
			mout = IO.do; 
			memok = 0b1; } } }
}

} /* test */

module iomodel
{
input		set;
input		di<16>;
input		sel;
input		read,rst;
output do<16>;
output setflag;
instrin		enable;

reg setdelay,flag,dreg<16>;

instruct enable par {
	setdelay:= set;
	setflag = flag;
	alt {
	^rst: par {
		flag := 0b0;
		setflag = flag;
		setdelay := 0b1; }
	else: par {
	 alt {
	  sel & read : do = dreg;
	  ^sel & read : do = 0b000000000000000 || flag; 
	  else: do = 0x0000;}
	 alt {
	  set & ^setdelay : par { dreg := di; flag := 0b1; } 
	  sel & read : flag := 0b0; } } }
}	
}

module delay {
	input start,rst;
	output pulse;
	instrin enable;
	reg dl1, dl2, dl3 ;
	instruct enable par {
		pulse = dl3;
		alt{
		^rst | dl3: par{ dl1 :=0b0; dl2:=0b0; dl3:=0b0; }
		else: par{
			dl1 := start;
			dl2 := dl1;
			dl3 := dl2; } } }
}