/*
 *	cache memory
 */
declare dram {
	input       ad<10>;
	input       di<16>;
	input       oe,we0,we1,rst;
	output      do<16>;
	instrout    dmemok;
	instrin     enable;
	instr_arg enable(ad,di,oe,we0,we1,rst); }

declare c_mem {
	input       ad<6>;
	input       di<16>;
	output      do<16>;
	input       we<2>;
	instrin     enable;
	instr_arg enable(ad,di,we); }

declare t_mem {
	input		we, ad<3>;
	input		di<5>;
	output		do<5>;
	instrin		enable;
	instr_arg enable(ad,di,we); }

declare dmapc {
	input  cpuoe, cpuwe0, cpuwe1, rst;
	input  cpuadr<10>, cpuwd<16>, tag<5>, dramdo<16>, dmemok;
	instrout cmwe0, cmwe1, cmemok, tmwe, dmoe, dmwe0, dmwe1;
	output cmemadr<6>,cmemdi<16>,dramadr<10>,wbufwd<16>;
	instrin     enable;
	instr_arg enable(cpuadr, cpuwd, tag, dramdo, dmemok,
			cpuoe, cpuwe0, cpuwe1, rst); }

module cache {
	input	rst, cpuadr<10>, cpuwd<16>, cpuwe0, cpuwe1, cpuoe;
	output	cpurd<16>, cpumemok;
	instrin	enable;

	dmapc		CC;
	dram		DRAM;
	c_mem  		CMEM;
	t_mem		TMEM;

instruct enable par {
	CC.enable(cpuadr, cpuwd, TMEM.do, DRAM.do, DRAM.dmemok,
		cpuoe, cpuwe0, cpuwe1, rst);
	CMEM.enable(CC.cmemadr, CC.cmemdi, CC.cmwe0||CC.cmwe1);
	DRAM.enable(CC.dramadr, CC.wbufwd, CC.dmoe, CC.dmwe0, CC.dmwe1, rst);
	TMEM.enable(cpuadr<5:3>,0b1||cpuadr<9:6>,CC.tmwe);
	cpurd = CMEM.do; cpumemok = CC.cmemok;
}

} /* cache */

circuit c_mem {
	input       ad<6>;
	input       di<16>;
	output      do<16>;
	input       we<2>;
	instrin     enable;
	mem     memory[64]<8>;

	instruct enable par {
		do =  memory[ad & 0b111110] || memory[ad | 0b000001] ;
		alt {we<0>: memory[ad & 0b111110] := di<15:8>; }
		alt {we<1>: memory[ad | 0b000001] := di<7:0>; }
	}
} /* cache memory */

circuit t_mem {
	input		we,ad<3>;
	input		di<5>;
	output		do<5>;
	instrin		enable;
	mem			memory[8]<5>;

	instruct enable par {
			do = memory[ad];
			alt{ we: memory[ad]:=di; }
	}
} /* tag memory */