/* * btest.sfl */ declare bpico16 { input datain<16>; input rst; output dataout<16>; output address<16>; instrout oe,we; instrin enable; instr_arg enable(datain, rst); } declare memory { input ad<8>; input dih<8>, dil<8>; output do<16>; instrin oe, we0, we1; instr_arg oe(ad); instr_arg we0(ad, dih); instr_arg we1(ad, dil); } circuit memory { input ad<8>; input dih<8>, dil<8>; output do<16>; instrin oe, we0, we1; mem memory[256]<8>; instruct oe do = memory[ad & 0b11111110] || memory[ad | 0b00000001] ; instruct we0 memory[ad & 0b11111110] := dih; instruct we1 memory[ad | 0b00000001] := dil; } /* memory */ module btest { input rst; instrin enable; bpico16 PICO; memory MEMORY; sel_v mout<16>; /* memory output */ sel_v we,oe; /* memory write enable */ instruct enable par { PICO.enable(mout, rst); we = PICO.we; oe = PICO.oe; mout = MEMORY.oe(PICO.address<7:0>).do; alt { we: par {MEMORY.we0(PICO.address<7:0>, PICO.dataout<15:8>); MEMORY.we1(PICO.address<7:0>, PICO.dataout<7:0>);} } } } /* test */