declare datapath2 {
	input		datain<4>, com<4>;
	output		accout<4>;
	instrout    we;
	instrin		enable;
	instr_arg	enable(com, datain);
}

declare memory {
	input		ad<4>;
	input		di<4>;
	output		do<4>;
	instrin		oe, we;
	instr_arg	oe(ad);
	instr_arg	we(ad, di);
}

circuit memory {
	input		ad<4>;
	input		di<4>;
	output		do<4>;
	instrin		oe,we;

	mem		memory[16]<4>;

	instruct oe do = memory[ad] ;
	instruct we memory[ad] := di;
} /* memory */

module testdp2 {
instrin		enable;
input 		com<4>, adr<4>;

datapath2	ACCUM;
memory		MEMORY;

sel_v		do<4>;
sel_v		di<4>;

instruct enable par {
	do = ACCUM.enable(com, di).accout;
	alt {ACCUM.we : MEMORY.we(adr,do); }
	di = MEMORY.oe(adr).do;
}

} /* test */