declare am2 {
	input		datain<8>, rst;
	output		accout<4>, addr<4>;
	instrin		enable;
	instrout    we;
	instr_arg	enable(datain,rst);
}

declare memory {
	input		ad<4>;
	input		di<4>;
	output		do<8>;
	instrin		oe, we;
	instr_arg oe(ad);
	instr_arg we(ad,di);
}

module testam2 {
instrin		enable;
input		rst;

am2	ACCUM;
memory		MEMORY;

sel_v 		datard<8>, datawr<4>, addr<4>;

instruct enable par {
	datard = MEMORY.oe(addr).do;
	datawr = ACCUM.enable(datard,rst).accout;
	alt{ ACCUM.we: MEMORY.we(addr, datawr); };
	addr = ACCUM.addr;
}

} /* test */
circuit memory {
	input		ad<4>;
	input		di<4>;
	output		do<8>;
	instrin		oe,we;
	mem		memory[16]<8>;
	instruct oe do = memory[ad] ;
	instruct we memory[ad] := 0b0000 || di;
} /* memory */