declare alu4 {
		input ina<4>, inb<4>, com<3>;
		output y<4> ;
		instrin enable ;
		instr_arg enable(ina, inb, com);
}
declare addsub4 {
	input ina<4>, inb<4>, sub ;
	output sumdiff<4> ;
	instrin enable ;
	instr_arg enable(ina, inb, sub);
}
declare fadder {
	input a, b, ci ;
	output s, co ;
	instrin enable ;
	instr_arg enable(a, b, ci);
}

module datapath1{
input datain<4>, com<3> ;
output accout<4> ;
instrin enable ;
reg acc<4> ;
alu4 alu;
instruct enable par{
	accout = acc ;
	acc := alu.enable(acc, datain, com).y;
}
}

module alu4{

input ina<4>, inb<4>, com<3> ;
output y<4> ;
instrin enable ;
addsub4 as4 ;
instruct enable alt { 
	com==0b000: y = ina ;		/* Through A */
	com==0b001: y = inb ;		/* Through B */
	com==0b010: y = ina & inb ;	/* A and B */
	com==0b011: y = ina | inb ;	/* A or B */
 	com==0b100: y = ina<2>||ina<1>||ina<0>|| 0b0 ;	/* Left Shift */
  	com==0b101: y = 0b0 || ina<3>||ina<2>||ina<1> ;	/* Right shift */
	  else: 	y = as4.enable(ina, inb, com<0>).sumdiff ; /* SUB/ADD */
}
}

module addsub4{

input ina<4>, inb<4>, sub ;
output sumdiff<4> ;
instrin enable ;
sel c0,c1,c2,st3,st2,st1,st0, bb<4> ;
fadder fa0, fa1, fa2, fa3 ;
instruct enable par {
	alt { sub: bb = ^inb ;
		else: bb = inb ; }
	st0 = fa0.enable(ina<0>, bb<0>, sub).s;
	c0 = fa0.enable(ina<0>,bb<0>, sub).co;
	st1 = fa1.enable(ina<1>, bb<1>, c0).s;
	c1 = fa1.enable(ina<1>, bb<1>, c0).co;
	st2 = fa2.enable(ina<2>, bb<2>, c1).s;
	c2 = fa2.enable(ina<2>, bb<2>, c1).co;
	st3 = fa3.enable(ina<3>, bb<3>, c2).s;
	sumdiff = st3||st2||st1||st0;
}
}
/**************************/
/*	1bit Full adder       */
/**************************/
module fadder {
    input a, b, ci ;
    output s, co ;
    instrin enable ;
    instruct enable par {
    s = (a & ^b & ^ci)|(^a & b & ^ci)|(^a & ^b & ci)|(a & b & ci) ;
	co = (a & b )|(b & ci)|(a & ci) ;
	}
}