/*
 *	cache memory
 */
%d INIT   0b000000001
%d WAIT1  0b000000010
%d WAIT2  0b000000100
%d WAIT3  0b000001000
%d FIRST  0b000010000
%d SECOND 0b000100000
%d THIRD  0b001000000
%d FORTH  0b010000000
%d IWAIT  0b100000000
declare main_mem {
	input       ad<10>;
	input       di<16>;
	output      do<16>;
	input       we<2>;
	instrin     enable;
	instr_arg enable(ad,di,we); }

module dram {
	input       ad<10>;
	input       di<16>;
	output      do<16>;
	input       oe,we0,we1,rst;
	instrin     enable;
	instrout    dmemok,dmemwok;
	main_mem	MM;
	reg stat<9>;

	instruct enable alt {
	^rst: stat := INIT;
	else: alt {
	  stat == INIT: par{ dmemwok(); do=0x0000; 
						alt {oe|we0|we1: stat := WAIT1; }}
	  stat == WAIT1: par{stat:=WAIT2;do=0x0000;}
	  stat == WAIT2: par{stat:=FIRST;do=0x0000;}
	  stat == FIRST: alt {we0|we1: par {MM.enable(ad, di, we0||we1);
									dmemok(); stat := INIT; } 
	                 else: par {do=MM.enable(ad<9:3>||0b000, di, 0b00).do;
								dmemok(); stat := SECOND;}}
	  stat == SECOND: par{ do=MM.enable(ad<9:3>||0b010,di,0b00).do;
							dmemok(); stat := THIRD;}
	  stat == THIRD: par{ do=MM.enable(ad<9:3>||0b100,di,0b00).do;
							dmemok(); stat := FORTH;}
	  stat == FORTH: par{ do=MM.enable(ad<9:3>||0b110,di,0b00).do;
							dmemok(); stat := IWAIT;}
	  stat == IWAIT: par{stat := INIT;do=0x0000;}}
	  }
}

circuit main_mem {
	input       ad<10>;
	input       di<16>;
	output      do<16>;
	input       we<2>;
	instrin     enable;
	mem     memory[1024]<8>;

	instruct enable par {
		do =  memory[ad & 0b1111111110] || memory[ad | 0b0000000001] ;
		alt {we<0>: memory[ad & 0b1111111110] := di<15:8>; }
		alt {we<1>: memory[ad | 0b0000000001] := di<7:0>; }
	}
} /* main memory */