/*
 *	Direct map write through cache controller
 */
%d CINIT  0b0001
%d CWAIT  0b0010
%d CREAD  0b0100
%d CWWAIT 0b1000

declare cup4 {
input rst,up;
output c<2>;
instrin enable;
instr_arg enable(rst,up); }

module dmapc {
input  cpuoe, cpuwe0, cpuwe1, rst;
input  cpuadr<10>, cpuwd<16>, tag<5>, dramdo<16>, dmemok;
output cmemadr<6>, cmemdi<16>, dramadr<10>, wbufwd<16>;
instrout cmwe0, cmwe1, cmemok, tmwe, dmoe, dmwe0, dmwe1;
instrin		enable;
reg			stat<4>, wbuf<16>, abuf<10>, dmemwe<2>;
sel 		hit;
cup4	CT;
instrself cup, crst;

instruct enable par {
	CT.enable(crst,cup); wbufwd = wbuf; dramadr = abuf; 
  	hit = tag<4> & ^(/|(cpuadr<9:6> @ tag<3:0>)); 
	alt { ^rst: par {stat := CINIT; cmemadr= cpuadr<5:0>;
		wbuf := 0x0000; abuf := 0b0000000000;
							dmemwe := 0b00; crst(); }
	else:
	 alt{ 
	  stat==CINIT : par{ cmemadr = cpuadr<5:0>; cmemdi = cpuwd; alt{
	     cpuoe: alt {hit: cmemok(); 
				     else: par{ crst(); dmoe(); abuf := cpuadr;
								stat := CWAIT;} } 
		(cpuwe0 | cpuwe1): par { 
		   cmemok(); alt{ hit: par{ alt{ cpuwe0: cmwe0();}
									alt{ cpuwe1: cmwe1();} } }
		   wbuf := cpuwd; abuf := cpuadr;
		   dmemwe := cpuwe1||cpuwe0; stat := CWWAIT;} }}
	  stat==CWAIT : par{ cmemadr = cpuadr<5:3>||CT.c||0b0; cmemdi = dramdo;
		alt {dmemok: par{cmwe0(); cmwe1(); cup(); 
						alt{ CT.c == 0b11: stat :=CREAD;} } }}
	  stat==CREAD : par{cmemadr = cpuadr<5:0>; cmemdi = cpuwd;
						tmwe(); cmemok(); stat:=CINIT;} 
	  stat==CWWAIT : par { cmemadr = cpuadr<5:0>; cmemdi = cpuwd;
						   alt { dmemwe<0>: dmwe0();}
						   alt { dmemwe<1>: dmwe1();} 
						   alt{dmemok: stat := CINIT;}} }
    }} /* test */
}
module cup4 {
input rst,up;
output c<2>;
instrin enable;

reg count<2>;
instruct enable par {
	c = count; alt{
	rst: count := 0b00;
	else: alt{ up: alt{
	count==0b00: count := 0b01;
	count==0b01: count := 0b10;
	count==0b10: count := 0b11;
	count==0b11: count := 0b00; } } } }
}