/*
 *	test.sfl
 */

declare pico16 {
	input		datain<16>;
	input		int_req;
	input		rst;
	output		dataout<16>;
	output		address<16>;
	instrout	oe, we0, we1;
	instrin		enable;
	instr_arg enable(datain, int_req, rst);
}

declare memory {
	input       ad<8>;
	input       dih<8>, dil<8>;
	output      do<16>;
	instrin     oe, we0, we1;
	instr_arg    oe(ad);
	instr_arg    we0(ad, dih);
	instr_arg    we1(ad, dil);
}

circuit memory {
	input       ad<8>;
	input       dih<8>, dil<8>;
	output      do<16>;
	instrin     oe, we0, we1;
	mem     memory[256]<8>;
	instruct oe do =  memory[ad & 0b11111110] || memory[ad | 0b00000001] ;
	instruct we0 memory[ad & 0b11111110] := dih;
	instruct we1 memory[ad | 0b00000001] := dil;
} /* memory */
								
declare iomodel {
	input		set;
	input		di<16>;
	input		sel;
	input		read, rst;
	output do<16>;
	output setflag;
	instrin		enable;
	instr_arg enable(set, di, sel, read, rst);
}

module test {

input ioset;
input iodata<16>;
input rst;
instrin enable;
pico16		PICO;
memory		MEMORY;
iomodel		IO;

sel_v		mout<16>; /* memory output */
sel_v		intrq; 

instruct enable par {
	PICO.enable(mout, intrq, rst);
	intrq = IO.enable(ioset, iodata, PICO.address<1>, 
			PICO.oe & PICO.address<15>, rst).setflag;
	alt { ^PICO.address<15>: 
	  any {PICO.we0: MEMORY.we0(PICO.address<7:0>, PICO.dataout<15:8>);
	       PICO.we1: MEMORY.we1(PICO.address<7:0>, PICO.dataout<7:0>);}}
	alt { 
	   ^PICO.address<15> : mout = MEMORY.oe(PICO.address<7:0>).do;
	   else: mout = IO.do; }
	}
} /* test */

module iomodel
{
input		set;
input		di<16>;
input		sel;
input		read,rst;
output do<16>;
output setflag;
instrin		enable;

reg setdelay,flag,dreg<16>;

instruct enable par {
	setdelay:= set;
	setflag = flag;
	alt {
	^rst: par {
		flag := 0b0;
		setflag = flag;
		setdelay := 0b1; }
	else: par {
	 alt {
	  sel & read : do = dreg;
	  ^sel & read : do = 0b000000000000000 || flag; 
	  else: do = 0x0000;}
	 alt {
	  set & ^setdelay : par { dreg := di; flag := 0b1; } 
	  sel & read : flag := 0b0; } } }
}	
}