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             Version D-2010.03 for linux -- Feb 22, 2010
              Copyright (c) 1988-2009 by Synopsys, Inc.
                         ALL RIGHTS RESERVED

This software and the associated documentation are confidential and 
proprietary to Synopsys, Inc. Your use or disclosure of this software 
is subject to the terms and conditions of a written license agreement 
between you, or your company, and Synopsys, Inc.

The above trademark notice does not imply that you are licensed to use 
all of the listed products. You are licensed to use only those products 
for which you have lawfully obtained a valid license key.

Initializing...
set search_path [concat "/home/cad/lib/osu_stdcells/lib/tsmc018/lib/" $search_path]
/home/cad/lib/osu_stdcells/lib/tsmc018/lib/ . /home/vdec/synopsys/syn-2010.03/libraries/syn /home/vdec/synopsys/syn-2010.03/dw/syn_ver /home/vdec/synopsys/syn-2010.03/dw/sim_ver
set LIB_MAX_FILE {osu018_stdcells.db  }
osu018_stdcells.db  
set link_library $LIB_MAX_FILE
osu018_stdcells.db  
set target_library $LIB_MAX_FILE
osu018_stdcells.db  
read_verilog alu.v
Loading db file '/home/cad/lib/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db'
Loading db file '/home/vdec/synopsys/syn-2010.03/libraries/syn/gtech.db'
Loading db file '/home/vdec/synopsys/syn-2010.03/libraries/syn/standard.sldb'
  Loading link library 'osu018_stdcells'
  Loading link library 'gtech'
Loading verilog file '/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/alu.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Opening include file def.h
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/alu.v
Opening include file def.h
Presto compilation completed successfully.
Current design is now '/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/alu.db:alu'
Loaded 1 design.
Current design is 'alu'.
alu
read_verilog rfile.v
Loading verilog file '/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/rfile.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Opening include file def.h
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/rfile.v
Opening include file def.h

Statistics for case statements in always block at line 26 in file
	'/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/rfile.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            28            |    auto/auto     |
===============================================

Inferred memory devices in process
	in routine rfile line 26 in file
		'/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/rfile.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       r0_reg        | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|       r2_reg        | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|       r1_reg        | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|       r7_reg        | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|       r3_reg        | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|       r4_reg        | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|       r5_reg        | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
|       r6_reg        | Flip-flop |  16   |  Y  | N  | N  | N  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Current design is now '/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/rfile.db:rfile'
Loaded 1 design.
Current design is 'rfile'.
rfile
read_verilog poco_2c.v
Loading verilog file '/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/poco_2c.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Opening include file def2.h
Reading with Presto HDL Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/poco_2c.v
Opening include file def2.h

Statistics for case statements in always block at line 88 in file
	'/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/poco_2c.v'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            92            |     no/auto      |
===============================================

Inferred memory devices in process
	in routine poco line 76 in file
		'/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/poco_2c.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       pc_reg        | Flip-flop |  16   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine poco line 82 in file
		'/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/poco_2c.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       ir_reg        | Flip-flop |  16   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

Inferred memory devices in process
	in routine poco line 88 in file
		'/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/poco_2c.v'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      stat_reg       | Flip-flop |   1   |  N  | N  | Y  | N  | N  | N  | N  |
|      stat_reg       | Flip-flop |   1   |  N  | N  | N  | Y  | N  | N  | N  |
===============================================================================
Presto compilation completed successfully.
Current design is now '/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/poco.db:poco'
Loaded 1 design.
Current design is 'poco'.
poco
current_design "poco"
Current design is 'poco'.
{poco}
create_clock -period 4.0 clk 
1
set_input_delay 2.5 -clock clk [find port "datain*"]
1
set_output_delay 2.5 -clock clk [find port "addr*"]
1
set_output_delay 2.5 -clock clk [find port "dataout*"]
1
set_output_delay 2.5 -clock clk [find port "we"]
1
set_max_fanout 12 [current_design]
Current design is 'poco'.
1
set_max_area 0
1
compile -map_effort medium -area_effort medium
Information: Evaluating DesignWare library utilization. (UISN-27)

============================================================================
| DesignWare Building Block Library       |      Version       | Available |
============================================================================
| Basic DW Building Blocks                | D-2010.03-DWBB_1003 |    *     |
| Licensed DW Building Blocks             |                    |           |
============================================================================


Information: There are 2 potential problems in your design. Please run 'check_design' for more information. (LINT-99)



  Beginning Pass 1 Mapping
  ------------------------
  Processing 'rfile'
  Processing 'alu'
  Processing 'poco'

  Updating timing information
Information: Updating design information... (UID-85)

  Beginning Implementation Selection
  ----------------------------------
  Processing 'alu_DW01_sub_0'
  Processing 'alu_DW01_add_0'

  Beginning Mapping Optimizations  (Medium effort)
  -------------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:04   58930.0      0.00       0.0     101.0                          
    0:00:04   58930.0      0.00       0.0     101.0                          
    0:00:04   58930.0      0.00       0.0     101.0                          
    0:00:04   58930.0      0.00       0.0     101.0                          
    0:00:04   58930.0      0.00       0.0     101.0                          
    0:00:04   57233.0      0.41       9.5     101.0                          
    0:00:04   57361.0      0.00       0.0     101.0                          
    0:00:04   57249.0      0.16       3.0      97.0                          
    0:00:04   57386.0      0.04       0.3      96.0                          
    0:00:04   57298.0      0.05       0.7      96.0                          
    0:00:04   57337.0      0.00       0.0      94.0                          
    0:00:04   57329.0      0.00       0.0      94.0                          
    0:00:04   57329.0      0.00       0.0      94.0                          
    0:00:04   57329.0      0.00       0.0      94.0                          
    0:00:04   57329.0      0.00       0.0      94.0                          
    0:00:04   57329.0      0.00       0.0      94.0                          
    0:00:05   57585.0      0.00       0.0      36.0                          
    0:00:05   57681.0      0.00       0.0      16.0                          
    0:00:05   57713.0      0.00       0.0       8.0                          
    0:00:05   57745.0      0.00       0.0       0.0                          
    0:00:05   57745.0      0.00       0.0       0.0                          
    0:00:05   57745.0      0.00       0.0       0.0                          
    0:00:05   57745.0      0.00       0.0       0.0                          



  Beginning Delay Optimization Phase
  ----------------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:05   57745.0      0.00       0.0       0.0                          
    0:00:05   57745.0      0.00       0.0       0.0                          
    0:00:05   57745.0      0.00       0.0       0.0                          


  Beginning Area-Recovery Phase  (max_area 0)
  -----------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:05   57745.0      0.00       0.0       0.0                          
    0:00:05   57745.0      0.00       0.0       0.0                          
    0:00:05   57041.0      0.00       0.0       0.0                          
    0:00:05   56785.0      0.00       0.0       0.0                          
    0:00:05   56737.0      0.00       0.0       0.0                          
    0:00:05   56721.0      0.00       0.0       0.0                          
    0:00:05   56705.0      0.00       0.0       0.0                          
    0:00:05   56705.0      0.00       0.0       0.0                          
    0:00:05   56705.0      0.00       0.0       0.0                          
    0:00:05   56705.0      0.00       0.0       0.0                          
    0:00:05   56705.0      0.00       0.0       0.0                          
    0:00:05   56705.0      0.00       0.0       0.0                          
    0:00:05   56705.0      0.00       0.0       0.0                          
    0:00:05   56705.0      0.00       0.0       0.0                          
    0:00:05   56633.0      0.00       0.0       0.0                          
    0:00:05   56633.0      0.00       0.0       0.0                          
    0:00:05   56633.0      0.00       0.0       0.0                          
    0:00:05   56633.0      0.00       0.0       0.0                          
    0:00:05   56633.0      0.00       0.0       0.0                          
    0:00:05   56633.0      0.00       0.0       0.0                          
    0:00:05   56633.0      0.00       0.0       0.0                          
    0:00:05   56633.0      0.00       0.0       0.0                          
Loading db file '/home/cad/lib/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db'

  Optimization Complete
  ---------------------
1
report_timing -max_paths 10
Information: Updating graph... (UID-83)
Information: Updating design information... (UID-85)
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 10
Design : poco
Version: D-2010.03
Date   : Tue Dec 17 15:53:28 2013
****************************************

Operating Conditions: typical   Library: osu018_stdcells
Wire Load Model Mode: top

  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r0_reg[14]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U7/Y (XNOR2X1)                              0.12       3.14 r
  alu_1/add_7/SUM[14] (alu_DW01_add_1)                    0.00       3.14 r
  alu_1/U129/Y (AOI22X1)                                  0.08       3.22 f
  alu_1/U137/Y (NAND3X1)                                  0.13       3.34 r
  alu_1/y[14] (alu)                                       0.00       3.34 r
  U438/Y (AOI22X1)                                        0.06       3.40 f
  U440/Y (NAND2X1)                                        0.28       3.68 r
  rfile_1/c[14] (rfile)                                   0.00       3.68 r
  rfile_1/U574/Y (MUX2X1)                                 0.08       3.76 f
  rfile_1/U72/Y (INVX1)                                   0.05       3.81 r
  rfile_1/r0_reg[14]/D (DFFPOSX1)                         0.00       3.81 r
  data arrival time                                                  3.81

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r0_reg[14]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.81
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r1_reg[14]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U7/Y (XNOR2X1)                              0.12       3.14 r
  alu_1/add_7/SUM[14] (alu_DW01_add_1)                    0.00       3.14 r
  alu_1/U129/Y (AOI22X1)                                  0.08       3.22 f
  alu_1/U137/Y (NAND3X1)                                  0.13       3.34 r
  alu_1/y[14] (alu)                                       0.00       3.34 r
  U438/Y (AOI22X1)                                        0.06       3.40 f
  U440/Y (NAND2X1)                                        0.28       3.68 r
  rfile_1/c[14] (rfile)                                   0.00       3.68 r
  rfile_1/U548/Y (MUX2X1)                                 0.08       3.76 f
  rfile_1/U74/Y (INVX1)                                   0.05       3.81 r
  rfile_1/r1_reg[14]/D (DFFPOSX1)                         0.00       3.81 r
  data arrival time                                                  3.81

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r1_reg[14]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.81
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r2_reg[14]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U7/Y (XNOR2X1)                              0.12       3.14 r
  alu_1/add_7/SUM[14] (alu_DW01_add_1)                    0.00       3.14 r
  alu_1/U129/Y (AOI22X1)                                  0.08       3.22 f
  alu_1/U137/Y (NAND3X1)                                  0.13       3.34 r
  alu_1/y[14] (alu)                                       0.00       3.34 r
  U438/Y (AOI22X1)                                        0.06       3.40 f
  U440/Y (NAND2X1)                                        0.28       3.68 r
  rfile_1/c[14] (rfile)                                   0.00       3.68 r
  rfile_1/U561/Y (MUX2X1)                                 0.08       3.76 f
  rfile_1/U73/Y (INVX1)                                   0.05       3.81 r
  rfile_1/r2_reg[14]/D (DFFPOSX1)                         0.00       3.81 r
  data arrival time                                                  3.81

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r2_reg[14]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.81
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r3_reg[14]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U7/Y (XNOR2X1)                              0.12       3.14 r
  alu_1/add_7/SUM[14] (alu_DW01_add_1)                    0.00       3.14 r
  alu_1/U129/Y (AOI22X1)                                  0.08       3.22 f
  alu_1/U137/Y (NAND3X1)                                  0.13       3.34 r
  alu_1/y[14] (alu)                                       0.00       3.34 r
  U438/Y (AOI22X1)                                        0.06       3.40 f
  U440/Y (NAND2X1)                                        0.28       3.68 r
  rfile_1/c[14] (rfile)                                   0.00       3.68 r
  rfile_1/U516/Y (MUX2X1)                                 0.08       3.76 f
  rfile_1/U76/Y (INVX1)                                   0.05       3.81 r
  rfile_1/r3_reg[14]/D (DFFPOSX1)                         0.00       3.81 r
  data arrival time                                                  3.81

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r3_reg[14]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.81
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r4_reg[14]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U7/Y (XNOR2X1)                              0.12       3.14 r
  alu_1/add_7/SUM[14] (alu_DW01_add_1)                    0.00       3.14 r
  alu_1/U129/Y (AOI22X1)                                  0.08       3.22 f
  alu_1/U137/Y (NAND3X1)                                  0.13       3.34 r
  alu_1/y[14] (alu)                                       0.00       3.34 r
  U438/Y (AOI22X1)                                        0.06       3.40 f
  U440/Y (NAND2X1)                                        0.28       3.68 r
  rfile_1/c[14] (rfile)                                   0.00       3.68 r
  rfile_1/U503/Y (MUX2X1)                                 0.08       3.76 f
  rfile_1/U77/Y (INVX1)                                   0.05       3.81 r
  rfile_1/r4_reg[14]/D (DFFPOSX1)                         0.00       3.81 r
  data arrival time                                                  3.81

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r4_reg[14]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.81
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r5_reg[14]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U7/Y (XNOR2X1)                              0.12       3.14 r
  alu_1/add_7/SUM[14] (alu_DW01_add_1)                    0.00       3.14 r
  alu_1/U129/Y (AOI22X1)                                  0.08       3.22 f
  alu_1/U137/Y (NAND3X1)                                  0.13       3.34 r
  alu_1/y[14] (alu)                                       0.00       3.34 r
  U438/Y (AOI22X1)                                        0.06       3.40 f
  U440/Y (NAND2X1)                                        0.28       3.68 r
  rfile_1/c[14] (rfile)                                   0.00       3.68 r
  rfile_1/U482/Y (MUX2X1)                                 0.08       3.76 f
  rfile_1/U78/Y (INVX1)                                   0.05       3.81 r
  rfile_1/r5_reg[14]/D (DFFPOSX1)                         0.00       3.81 r
  data arrival time                                                  3.81

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r5_reg[14]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.81
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r6_reg[14]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U7/Y (XNOR2X1)                              0.12       3.14 r
  alu_1/add_7/SUM[14] (alu_DW01_add_1)                    0.00       3.14 r
  alu_1/U129/Y (AOI22X1)                                  0.08       3.22 f
  alu_1/U137/Y (NAND3X1)                                  0.13       3.34 r
  alu_1/y[14] (alu)                                       0.00       3.34 r
  U438/Y (AOI22X1)                                        0.06       3.40 f
  U440/Y (NAND2X1)                                        0.28       3.68 r
  rfile_1/c[14] (rfile)                                   0.00       3.68 r
  rfile_1/U463/Y (MUX2X1)                                 0.08       3.76 f
  rfile_1/U79/Y (INVX1)                                   0.05       3.81 r
  rfile_1/r6_reg[14]/D (DFFPOSX1)                         0.00       3.81 r
  data arrival time                                                  3.81

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r6_reg[14]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.81
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r7_reg[14]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U7/Y (XNOR2X1)                              0.12       3.14 r
  alu_1/add_7/SUM[14] (alu_DW01_add_1)                    0.00       3.14 r
  alu_1/U129/Y (AOI22X1)                                  0.08       3.22 f
  alu_1/U137/Y (NAND3X1)                                  0.13       3.34 r
  alu_1/y[14] (alu)                                       0.00       3.34 r
  U438/Y (AOI22X1)                                        0.06       3.40 f
  U440/Y (NAND2X1)                                        0.28       3.68 r
  rfile_1/c[14] (rfile)                                   0.00       3.68 r
  rfile_1/U535/Y (MUX2X1)                                 0.08       3.76 f
  rfile_1/U75/Y (INVX1)                                   0.05       3.81 r
  rfile_1/r7_reg[14]/D (DFFPOSX1)                         0.00       3.81 r
  data arrival time                                                  3.81

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r7_reg[14]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.81
  --------------------------------------------------------------------------
  slack (MET)                                                        0.00


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r4_reg[15]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U41/Y (AOI21X1)                             0.10       3.12 f
  alu_1/add_7/U39/Y (XNOR2X1)                             0.11       3.23 r
  alu_1/add_7/SUM[15] (alu_DW01_add_1)                    0.00       3.23 r
  alu_1/U147/Y (AOI21X1)                                  0.07       3.29 f
  alu_1/U148/Y (NAND3X1)                                  0.10       3.39 r
  alu_1/y[15] (alu)                                       0.00       3.39 r
  U441/Y (AOI22X1)                                        0.06       3.45 f
  U443/Y (NAND2X1)                                        0.07       3.53 r
  rfile_1/c[15] (rfile)                                   0.00       3.53 r
  rfile_1/U28/Y (BUFX4)                                   0.15       3.68 r
  rfile_1/U504/Y (MUX2X1)                                 0.06       3.74 f
  rfile_1/U70/Y (INVX1)                                   0.04       3.78 r
  rfile_1/r4_reg[15]/D (DFFPOSX1)                         0.00       3.78 r
  data arrival time                                                  3.78

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r4_reg[15]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.78
  --------------------------------------------------------------------------
  slack (MET)                                                        0.03


  Startpoint: ir_reg[5] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: rfile_1/r6_reg[15]
            (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                   0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  ir_reg[5]/CLK (DFFSR)                                   0.00       0.00 r
  ir_reg[5]/Q (DFFSR)                                     0.24       0.24 f
  U360/Y (BUFX2)                                          0.19       0.43 f
  rfile_1/badr[0] (rfile)                                 0.00       0.43 f
  rfile_1/U83/Y (INVX2)                                   0.10       0.53 r
  rfile_1/U96/Y (NAND3X1)                                 0.21       0.74 f
  rfile_1/U59/Y (INVX2)                                   0.08       0.83 r
  rfile_1/U51/Y (INVX2)                                   0.17       0.99 f
  rfile_1/U107/Y (OAI22X1)                                0.11       1.10 r
  rfile_1/U108/Y (NOR2X1)                                 0.07       1.17 f
  rfile_1/U109/Y (NAND3X1)                                0.11       1.28 r
  rfile_1/b[1] (rfile)                                    0.00       1.28 r
  U470/Y (AOI22X1)                                        0.07       1.35 f
  U471/Y (INVX2)                                          0.11       1.46 r
  alu_1/b[1] (alu)                                        0.00       1.46 r
  alu_1/add_7/B[1] (alu_DW01_add_1)                       0.00       1.46 r
  alu_1/add_7/U95/Y (OR2X2)                               0.14       1.60 r
  alu_1/add_7/U93/Y (NAND3X1)                             0.05       1.65 f
  alu_1/add_7/U14/Y (NAND2X1)                             0.18       1.82 r
  alu_1/add_7/U92/Y (NAND3X1)                             0.06       1.88 f
  alu_1/add_7/U91/Y (NAND3X1)                             0.17       2.06 r
  alu_1/add_7/U6/Y (INVX2)                                0.12       2.18 f
  alu_1/add_7/U74/Y (OAI21X1)                             0.10       2.27 r
  alu_1/add_7/U64/Y (NAND3X1)                             0.05       2.32 f
  alu_1/add_7/U63/Y (NAND2X1)                             0.13       2.44 r
  alu_1/add_7/U57/Y (INVX2)                               0.05       2.49 f
  alu_1/add_7/U56/Y (OAI21X1)                             0.15       2.64 r
  alu_1/add_7/U50/Y (INVX2)                               0.05       2.69 f
  alu_1/add_7/U49/Y (OAI21X1)                             0.15       2.83 r
  alu_1/add_7/U46/Y (INVX2)                               0.05       2.88 f
  alu_1/add_7/U45/Y (OAI21X1)                             0.14       3.02 r
  alu_1/add_7/U41/Y (AOI21X1)                             0.10       3.12 f
  alu_1/add_7/U39/Y (XNOR2X1)                             0.11       3.23 r
  alu_1/add_7/SUM[15] (alu_DW01_add_1)                    0.00       3.23 r
  alu_1/U147/Y (AOI21X1)                                  0.07       3.29 f
  alu_1/U148/Y (NAND3X1)                                  0.10       3.39 r
  alu_1/y[15] (alu)                                       0.00       3.39 r
  U441/Y (AOI22X1)                                        0.06       3.45 f
  U443/Y (NAND2X1)                                        0.07       3.53 r
  rfile_1/c[15] (rfile)                                   0.00       3.53 r
  rfile_1/U28/Y (BUFX4)                                   0.15       3.68 r
  rfile_1/U464/Y (MUX2X1)                                 0.06       3.74 f
  rfile_1/U80/Y (INVX1)                                   0.04       3.78 r
  rfile_1/r6_reg[15]/D (DFFPOSX1)                         0.00       3.78 r
  data arrival time                                                  3.78

  clock clk (rise edge)                                   4.00       4.00
  clock network delay (ideal)                             0.00       4.00
  rfile_1/r6_reg[15]/CLK (DFFPOSX1)                       0.00       4.00 r
  library setup time                                     -0.19       3.81
  data required time                                                 3.81
  --------------------------------------------------------------------------
  data required time                                                 3.81
  data arrival time                                                 -3.78
  --------------------------------------------------------------------------
  slack (MET)                                                        0.03


1
report_area
 
****************************************
Report : area
Design : poco
Version: D-2010.03
Date   : Tue Dec 17 15:53:28 2013
****************************************

Library(s) Used:

    osu018_stdcells (File: /home/cad/lib/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db)

Number of ports:               51
Number of nets:               458
Number of cells:              360
Number of references:          18

Combinational area:       38361.000000
Noncombinational area:    18272.000000
Net Interconnect area:      undefined  (No wire load specified)

Total cell area:          56633.000000
Total area:                 undefined
1
report_power
Loading db file '/home/cad/lib/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db'
Information: Propagating switching activity (low effort zero delay simulation). (PWR-6)
Warning: Design has unannotated primary inputs. (PWR-414)
Warning: Design has unannotated sequential cell outputs. (PWR-415)
 
****************************************
Report : power
        -analysis_effort low
Design : poco
Version: D-2010.03
Date   : Tue Dec 17 15:53:28 2013
****************************************


Library(s) Used:

    osu018_stdcells (File: /home/cad/lib/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db)


Operating Conditions: typical   Library: osu018_stdcells
Wire Load Model Mode: top


Global Operating Voltage = 1.8  
Power-specific unit information :
    Voltage Units = 1V
    Capacitance Units = 1.000000pf
    Time Units = 1ns
    Dynamic Power Units = 1mW    (derived from V,C,T units)
    Leakage Power Units = 1nW


  Cell Internal Power  =   5.5059 mW   (89%)
  Net Switching Power  = 679.6010 uW   (11%)
                         ---------
Total Dynamic Power    =   6.1855 mW  (100%)

Cell Leakage Power     = 102.1369 nW

1
write -hier -format verilog -output poco.vnet
Writing verilog file '/home/hunga/papers/Japanese/Lecture/system/verilog/code/multi/poco.vnet'.
1
quit
Information: Defining new variable 'compile_group_pull_control_logic'. (CMD-041)
Information: Defining new variable 'LIB_MAX_FILE'. (CMD-041)

Thank you...
